PowerESL Power Integrity Verification

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PowerESL Power Integrity Verification

• ComLSI Inc.
• www.comlsi.com

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Analysis Examples
Package simulation
Chip grid IR drop analysis
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ESL power stack co-simulation
View animation as a slide show
Two identical on-chip loads at left and right
chip includes an ANR (active noise regulator)
simulation at the load on the left.
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Cost-aware co-design optimization

• Front-end planning
• Metal resources, bus W
• Decoupling / on-die C
• Loop-L to pkg caps cap placement
  spatio-temporal effectivity
• Load placement / i(t)s, max droop points (x,y,t)
  
• Voltage Islands / Multi-core
• Package resonance, Grid Resonance
• Kit/System analyses / input to chip layout
  optimization

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PowerESL Methodology

• What it IS
• Multi-region Power Integrity analysis chip,
  pkg., brd. elmnts
• Full-wave dynamic analysis
• On-chip and off-chip resonance

• Is NOT
• Replacement for connectivity verification via
  static analysis
• A power estimation tool

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PowerESL how it works (1)

• Power distribution analysis is separated into
  local and global nets.
• In the symmetric global net energy is stored in
  the electro-magnetic field and dissipated as
  heat.
• In the local net almost all of the energy is
  stored in the electric field (de-cap). Inductive
  storage is minimal.

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PowerESL how it works (2)

• Each region is modelled as containing a
  continuous electromagnetic field.
• Potential variations are calculated everywhere on
  the chip, including dielectric spaces between
  wires on the two layer symmetric on-chip grid.
• Symmetry is used in the global net design to
  improve the power grid performance and reduce
  simulation times.

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PowerESL how it works (3

• Symmetry means that supply currents in the global
  grid are differential.
• The instantaneous current flowing into each chip
  region from the supply net is always equal to the
  return current.
• This is built into the grid design using closely
  coupled differential pairs and equal numbers of
  closely spaced short vias connecting active and
  passive circuits to the on-chip global grid.
• These connections can be verified using a
  separate static analysis tool.

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PowerESL how it works (4)

• Equations for transmission line differential
  pairs in the on-chip grid are combined and solved
  with an efficient parallel technique.
• Pkg. board connections are modelled by a
  network of differential transmission line pairs
  and de-caps similarly represented.

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Netlist view
TRAN 30e-9. PLOT 200. ACC 0.0040. PRINTNODE
ALL. On-chip grid (total cap 3nF)
size width space Rs L(/cm)
C(/cm2) Gbruce 0.15 0.16 0.0010 0.0273 0.045
10e-9 125e-9 dcdr location
size Ibruce 0.0200 0.1350 0.0500 0.0150 dcdr.txt
20 lfsr Ibruce 0.0800 0.0700 0.0200 0.0200
lfsr.txt 20 msbe Ibruce 0.0100 0.0100 0.0050
0.0050 msbe.txt 20 Ibruce 0.0300 0.0100 0.0050
0.0050 msbe.txt 20 Ibruce 0.0100 0.0500 0.0050
0.0050 msbe.txt 20 Ibruce 0.0100 0.1000 0.0050
0.0050 msbe.txt 20 Ibruce 0.1150 0.0100 0.0050
0.0050 msbe.txt 20 Ibruce 0.1350 0.0100 0.0050
0.0050 msbe.txt 20 Ibruce 0.1350 0.0500 0.0050
0.0050 msbe.txt 20 Ibruce 0.1350 0.1000 0.0050
0.0050 msbe.txt 20 Ring R L
C length (Ohms/cm) (H/cm) (F/cm)
(cm) T1 13 1 3.1 10e-9 4.9e-12 0.0800 T2 1
2 3.1 10e-9 4.9e-12 0.0100 T3 2 3 3.1
10e-9 4.9e-12 0.0100 T4 3 4 3.1 10e-9
4.9e-12 0.0400
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Results IO impact on Core Noise
The voltage regulators, connecting between the IO
Ring and the Core Grid are seen to become
significant noise injection nodes with the
inclusion of loads and the IO Ring. Pictures
above are snapshots of dynamic plots.
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Noise Redistribution with C-CAP
With the Corner Caps connecting into the Core
Grid (Picture on the right), the spatial and
temporal distribution of noise generated in the
chip changes, though the magnitude of maximum
noise reduces. C-Caps tied into the core actually
increases temporal noise within the core this
was verified with HSpice simulations
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IO Ring Noise w/CAP Placement
C-Caps At IO Ring Corners
At IO Ring Bond Wires
At IO Regulator Inputs
In the chip Core Grid
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Noise Dependence Grid Components

• With a fixed on-chip capacitance value, increases
  in grid wire widths (reduction in resistance with
  minimal benefit in inductance) reduces noise to a
  point
• Increase in capacitance on-die has a sub-linear
  benefit in maximum noise reduction more CAP is
  not always good

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Resonant effects
Single active circuit block in a 4x4mm IC
resonance

• PowerESL results showing the effect of gate
  switching time and on-chip de-cap on maximum
  voltage droop.

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PowerESL Capacity

• The methodology is easily scalable to multiple
  regions within a die, such as independent cores
  OR multiple chips / pkgs.
• The granularity of analyses in controlled by load
  and decoupling granularity
• Due to inherent modelling simplifications,
  PowerESL is capable of analyzing full power
  delivery stacks including all essential R, L C
  components
• PowerESL is up to an order of magnitude faster in
  model development and analysis

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Not just a tool or any tool

• An expert service
• ComLSIs experts analyze and convert a high-level
  description of the power stack into a PowerESL
  model
• We run the simulations and optimization studies
  per your requirements
• We analyze and deliver the documented results
• Engagement
• 1 ComLSI expert for 3 weeks per chip
• IA architecture servers hosting a customer
  account
• You have remote access into the models, tool,
  analysis environment and documentation at all
  times

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Contact information

• ComLSI Inc.
• 6065 E. University Dr., C, Mesa, AZ 85207
• [phone] tel [phone] fax
  www.comlsi.com
• PowerESL team
• raj_at_comlsi.com [phone] (GMT 8)
• donald_at_comlsi.com [phone] (GMT)