Title: FPGA FFT Implementation
1FPGA FFT Implementation
East-West Design Test Symposium
Sergey Churayev, Bakhyt Matkarimov Kazakh-British
Technical University
September 21, 2009
21. Abstract
We consider FPGA design flow with C/C to
Verilog translation and verification and report
on FPGA implementation of fast Fourier transform
and Wiener filter for noise reduction of speech
signals on Xilinx Virtex-4
Efficient noise reduction of speech signals
is very important task in modern communications
systems. The main goal of this work is to
port into Verilog HDL C/C implementation of
spectral noise reduction with Wiener filter
32. Introduction
Input speech signal 8 KHz frequency Frames
32 sample length FFT 128-point Work
synchronous (sequential processing of
frames) Clock external
43. General structure of noise reduction test board
54. Block schema of noise reduction module
65. Main implementation issues
- Multiple clock domains
- Dual port RAM
- Handshake Protocol
- Conveyer optimization
- Synchronizing asynchronous events
- Synthesis of gating clock
- Finite state machine design
76. Multiple clock domains
- Why To maximize overall speed of data processing
-
- Different performance characteristics of FFT and
Wiener filter - modules
- FFT module 35 MHz clock frequency
- FFT Wiener filter 20 MHz clock frequency
- Implementation issues of multiple clock domains
- inter-domain synchronization
- data processing among all modules.
87. Dual port RAM
- Used as double sized data buffers for data
transfers between - connected modules. When previous module writes
output data - to one half of buffer, next module process
previously written - data from another half of buffer.
- Advantage
- read and write data operations at different
frequencies
98. Handshake Protocol
- Why To avoid collisions, when two modules trying
to access - data in one memory location.
- 4 states simple handshake protocol
- Initial (start transaction) state
- Request from Master
- Acknowledge from Slave
- Finish transaction from Master
109. Conveyer optimization
Increase clock frequency (overall speed) in
conveyer, transferring part of logic from
module with biggest time delay to module with
smallest time delay, when it is possible.
1110. Synchronizing asynchronous events
System operate synchronously with asynchronous
input signals. Flip-flop storage element can
enter to the metastable state, if data signals
are unstable in setuphold interval of preceding
clock edge or if the data pulse is too narrow.
Flip-flop metastability effect can reduced
1211. Synthesis of gating clock
Disable clock signal to reduce power waste FPGA
device using clock enable input signal
FPGA
ASIC
1312. Finite state machine design
RAMbased finite state machine Row address
represents the current state of the
machine Contents, associated with that address,
holds the output functions and the next state.
14THANK YOU FOR ATTENTION