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Subprograms

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George Mason University. ECE 448 FPGA and ASIC Design with VHDL. Subprograms. ECE 448 ... Attributes of Arrays & Array Types. 2. ECE 448 FPGA and ASIC ... – PowerPoint PPT presentation

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Title: Subprograms


1
Subprograms
ECE 448 Lecture 14
Attributes of Arrays Array Types
2
Unconstrained Array Types
3
Predefined Unconstrained Array Types
  • Predefined
  • bit_vector array of bits
  • string array of characters
  • Defined in the ieee.std_logic_1164 package
  • std_logic_vector array of std_logic_vectors

4
Predefined Unconstrained Array Types
  • subtype byte is bit_vector(7 downto 0)
  • .
  • variable channel_busy bit_vector(1 to 4)
  • .
  • constant ready_message string ready
  • .
  • signal memory_bus std_logic_vector (31 downto 0)

5
User-defined Unconstrained Array Types
  • type sample is array (natural range ltgt) of
    integer
  • .
  • variable long_sample is sample(0 to 255)
  • .
  • constant look_up_table_1 sample
  • (127, -45, 63, 23, 76)
  • .

6
Attributes of Arrays and Array Types
7
Array Attributes
  • Aleft(N) left bound of index range of dimension
    N of A
  • Aright(N) right bound of index range of
    dimension N of A
  • Alow(N) lower bound of index range of dimension
    N of A
  • Ahigh(N) upper bound of index range of dimension
    N of A
  • Arange(N) index range of dimension N of A
  • Areverse_range(N) index range of dimension N of
    A
  • Alength(N) length of index range of dimension N
    of A
  • Aascending(N) true if index range of dimension
    N of A
  • is an ascending range,
    false otherwise

8
Array Attributes - Examples
  • type A is array (1 to 4, 31 downto 0)
  • Aleft(1) 1
  • Aright(2) 0
  • Alow(1) 1
  • Ahigh(2) 31
  • Arange(1) 1 to 4
  • Alength(2) 32
  • Aascending(2) false

9
Subprograms
10
Subprograms
  • Include
  • functions and procedures
  • Commonly used pieces of code
  • Can be placed in a library, and then reused and
    shared among various projects
  • Abstract operations that are repeatedly performed
  • Type conversions
  • Use only sequential statements, the same as
    processes

11
Typical locations of subprograms
PACKAGE PACKAGE BODY
LIBRARY
global
ENTITY
FUNCTION / PROCEDURE
local for all architectures of a given entity
ARCHITECTURE Declarative part
local for a given architecture
12
Functions
13
Functions basic features
  • Functions
  • always return a single value as a result
  • are called using formal and actual parameters the
    same way as components
  • never modify parameters passed to them
  • parameters can only be constants (including
    generics) and signals (including ports)
  • variables are not allowed the default is a
    CONSTANT
  • when passing parameters, no range specification
    should be included (for example no RANGE for
    INTEGERS, or TO/DOWNTO for STD_LOGIC_VECTOR)
  • are always used in some expression, and not
    called on their own

14
Function syntax
  • FUNCTION function_name (ltparameter_listgt)
  • RETURN data_type IS
  • declarations
  • BEGIN
  • (sequential statements)
  • END function_name

15
Function parameters - example
  • FUNCTION f1
  • (a, b INTEGER SIGNAL c STD_LOGIC_VECTOR)
  • RETURN BOOLEAN IS
  • BEGIN
  • (sequantial statements)
  • END f1

16
Function calls - examples
  • x lt conv_integer(a)
  • IF x gt maximum(a, b) THEN ....
  • WHILE minimum(a, b) LOOP
  • .......

17
Function example (1)
  • library IEEE
  • use IEEE.std_logic_1164.all
  • ENTITY powerOfFour IS
  • PORT(
  • X IN INTEGER
  • Y OUT INTEGER
  • )
  • END powerOfFour

18
Function example (2)
  • ARCHITECTURE behavioral OF powerOfFour IS
  • FUNCTION Pow ( SIGNAL NINTEGER Exp
    INTEGER) RETURN INTEGER IS
  • VARIABLE Result INTEGER 1
  • BEGIN
  • FOR i IN 1 TO Exp LOOP
  • Result Result N
  • END LOOP
  • RETURN( Result )
  • END Pow
  • BEGIN
  • Y lt Pow(X, 4)
  • END behavioral

19
Package containing a function (1)
  • LIBRARY IEEE
  • USE IEEE.std_logic_1164.all
  • PACKAGE specialFunctions IS
  • FUNCTION Pow( SIGNAL N INTEGER Exp
    INTEGER) RETURN INTEGER
  • END specialFunctions

20
Package containing a function (2)
  • PACKAGE BODY specialFunctions IS
  • FUNCTION Pow(SIGNAL N INTEGER Exp INTEGER)
  • RETURN INTEGER IS
  • VARIABLE Result INTEGER 1
  • BEGIN
  • FOR i IN 1 TO Exp LOOP
  • Result Result N
  • END LOOP
  • RETURN( Result )
  • END Pow
  • END specialFunctions

21
Type conversion function (1)
  • LIBRARY ieee
  • USE ieee.std_logic_1164.all
  • --------------------------------------------------
    -----------------------------------------------
  • PACKAGE my_package IS
  • FUNCTION conv_integer (SIGNAL vector
    STD_LOGIC_VECTOR)
  • RETURN INTEGER
  • END my_package
  • --------------------------------------------------
    -----------------------------------------------

22
Type conversion function (2)
  • PACKAGE BODY my_package IS
  • FUNCTION conv_integer (SIGNAL vector
    STD_LOGIC_VECTOR)
  • RETURN INTEGER
  • VARIABLE result INTEGER RANGE 0 TO
    2vectorLENGTH - 1
  • VARIABLE carry STD_LOGIC
  • BEGIN
  • IF(vector(vectorHIGH)1 THEN result1
  • ELSE result 0
  • FOR i IN (vectorHIGH-1) DOWNTO
    (vectorLOW) LOOP
  • result result2
  • IF (vector(i) 1 THEN result
    result1
  • END IF
  • RETURN result
  • END conv_integer
  • END my_package

23
Type conversion function (3)
  • LIBRARY ieee
  • USE ieee.std_logic_1164.all
  • USE work.my_package.all
  • --------------------------------------------------
    -----------------------------------------------
  • ENTITY conv_int2 IS
  • PORT ( a IN STD_LOGIC_VECTOR (0 TO 3)
  • y OUT INTEGER RANGE 0 TO 15)
  • END conv_int2
  • --------------------------------------------------
    -----------------------------------------------
  • ARCHITECTURE my_arch OF conv_int2 IS
  • BEGIN
  • y lt conv_integer(a)
  • END my_arch

24
Procedures
25
Procedures basic features
  • Procedures
  • do not return a value
  • are called using formal and actual parameters the
    same way as components
  • may modify parameters passed to them
  • each parameter must have a mode IN, OUT, INOUT
  • parameters can be constants (including generics),
    signals (including ports), and variablesthe
    default for inputs (mode in) is a constant, the
    default for outputs (modes out and inout) is a
    variable
  • when passing parameters, range specification
    should be included (for example RANGE for
    INTEGERS, and TO/DOWNTO for STD_LOGIC_VECTOR)
  • Procedure calls are statements on their own

26
Procedure syntax
  • PROCEDURE procedure_name (ltparameter_listgt) IS
  • declarations
  • BEGIN
  • (sequential statements)
  • END function_name

27
Procedure parameters - example
  • PROCEDURE my_procedure
  • ( a IN BIT
  • SIGNAL b, c IN BIT
  • SIGNAL x OUT BIT_VECTOR(7 DOWNTO 0)
  • SIGNAL y INOUT INTEGER RANGE 0 TO 99) IS
  • BEGIN
  • (sequantial statements)
  • END my_procedure

28
Procedure calls - examples
  • compute_min_max(in1, in2, in3, out1, out2)
  • divide(dividend, divisor, quotient, remainder)
  • IF (a gt b) THEN
  • compute_min_max(in1, in2, in3, out1, out2)
  • .......

29
Procedure example (1)
  • LIBRARY ieee
  • USE ieee.std_logic_1164.all
  • ENTITY min_max IS
  • GENERIC (limit INTEGER 255)
  • PORT (
  • ena IN BIT
  • inp1, inp2 IN INTEGER RANGE 0 TO limit
  • min_out, max_out OUT INTEGER RANGE 0 TO
    limit)
  • )
  • END min_max

30
Procedure example (2)
  • ARCHITECTURE my_architecture OF min_max IS
  • PROCEDURE sort (SIGNAL in1, in2 IN INTEGER
    RANGE 0 TO limit
  • SIGNAL min, max
    OUT INTEGER RANGE 0 TO limit) IS
  • BEGIN
  • IF (in1 gt in2) THEN
  • max lt in1
  • min lt in2
  • ELSE
  • max lt in2
  • min lt in1
  • END IF
  • END sort
  • BEGIN
  • PROCESS (ena)
  • BEGIN
  • IF(ena1) THEN
  • sort (inp1, inp2, min_out,
    max_out)

31
Operators
32
Operator as a function (1)
  • LIBRARY ieee
  • USE ieee.std_logic_1164.al
  • --------------------------------------------------
    -----------------------------------------------
  • PACKAGE my_package IS
  • FUNCTION "" (a, b STD_LOGIC_VECTOR)
  • RETURN STD_LOGIC_VECTOR
  • END my_package
  • --------------------------------------------------
    -----------------------------------------------

33
Operator as a function (2)
  • PACKAGE BODY my_package IS
  • FUNCTION "" (a, b STD_LOGIC_VECTOR)
  • RETURN STD_LOGIC_VECTOR
  • VARIABLE result STD_LOGIC_VECTOR
  • VARIABLE carry STD_LOGIC
  • BEGIN
  • carry 0
  • FOR i IN aREVERSE_RANGE LOOP
  • result(i) a(i) XOR b(i) XOR carry
  • carry (a(i) AND b(i)) OR (a(i) AND
    carry) OR (b(i) AND carry))
  • END LOOP
  • RETURN result
  • END ""
  • END my_package

34
Operator Overloading
35
Operator overloading
  • Operator overloading allows different argument
    types for a given operation (function)
  • The VHDL tools resolve which of these functions
    to select based on the types of the inputs
  • This selection is transparent to the user as long
    as the function has been defined for the given
    argument types.

36
Different declarations for the same operator -
Example
  • Declarations in the package ieee.std_logic_unsigne
    d
  • function ( L std_logic_vector
    Rstd_logic_vector) return std_logic_vector
  • function ( L std_logic_vector R
    integer) return std_logic_vector
  • function ( L std_logic_vector
    Rstd_logic) return std_logic_vector

37
Different declarations for the same operator -
Example
  • signal count std_logic_vector(7 downto 0)
  • You can use
  • count lt count 0000_0001
  • or
  • count lt count 1
  • or
  • count lt count 1
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