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A Fast OnChip Decoupling Capacitance Allocation Method

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I=AV S. I. V. Violation region. Hot spot. Violation Region and Sampling Nodes ... Sampling nodes: (green)nodes with worst voltage drop, sampled one per tile in ... – PowerPoint PPT presentation

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Title: A Fast OnChip Decoupling Capacitance Allocation Method


1
A Fast On-Chip Decoupling Capacitance Allocation
Method
  • Min Zhao, Rajendran Panda,
  • Savithri Sundareswaran, Shu Yan, Yuhong Fu
  • Freescale Semiconductor Inc.

2
Outline
  • Decap allocation problem
  • Prior art
  • Our solution
  • Network reduction through macro-modeling
  • Decap optimization using charge-based sequence of
    linear programming (LP)
  • Experimental results
  • Summary

3
Decap Allocation Overview
  • Function
  • Suppress dynamic noise by supplying sudden
    current demands from local charge storage
  • Side effect of adding too much decap
  • Increased leakage
  • Increased die area
  • Risk of lower yield
  • Need to add minimum amount of decap, yet
    sufficient for reducing noise

4
Decap Allocation Problem
  • Formulated as a constrained optimization problem
  • Objective Identify decap locations and minimize
    the total decap to be added
  • Constraints
  • Voltage constraints voltage at all
    transistors/gates should be better than a
    specified threshold, at all time
  • Circuit system constraints KCL, KVL and circuit
    element equations
  • Decap constraints amount of decap allowed at a
    location is limited
  • Challenges
  • Power network is a multi-million element (RLC)
    circuit
  • Based on transient analysis result
  • The optimization problem is non-linear

5
Prior Art
  • Charge-based decap estimation
  • Method 1 (S. Zhao et al., TCAD 2002)
  • Sensitivity-based nonlinear optimization
  • Method 2 quadratic program (H. Su et al., TCAD
    2003)
  • Method 3 conjugate gradient solver(J. Fu et
    al., ASP-DAC 2003)
  • Method 4 fast conjugate gradient method(H. Li
    et al., DAC2005)
  • Method 5 sequence of linear programs(J. Fan et
    al., ISQED 2006)
  • Problem size reduction
  • Method 6 multi-grid method (K. Wang et al.,
    DAC2003)
  • Method 7 divide and conquer (H. Li et al., DAC
    2005)

6
Prior Art Charge-based Method
  • Method 1 (S. Zhao et al., TCAD 2002)
  • In initial iteration, decap is estimated for each
    module
  • through simple and approximate charge-based
    formula
  • Decap C (1 - 1/ ?) Q/Vthre ,
  • where ? max(1, V/Vthre) , Q ?0T I(t) dt
  • Then iteratively run transient analysis and
    increase decap, until Vthre are satisfied
  • Issues
  • May substantially over-estimation
  • Or may require multiple transient analysis
    iterations

7
Prior Art Sensitivity-based Method
  • Method 2-5
  • Compute sensitivity of voltage to decap placed at
    different locations and use sensitivity to guide
    the non-linear optimization
  • Issues
  • Many iterations of sensitivity calculation
  • One (adjoint) sensitivity calculation is
    equivalent to one expensive transient analysis

8
Prior Art Problem Size Reduction
  • Method 6
  • With multi-grid like method
  • Issues
  • Applied only to regular grid
  • Method 7
  • Partition the power network
  • Each partition is solved by a sensitivity-based
    non-linear optimizer
  • Issues
  • The assumption that partition boundary voltage is
    not affected by decap may introduce error
  • Partition size becomes very large when one hot
    spot cover large area

9
Our Solution
10
Background Macro-modeling
  • Matrix equations for the unreduced power network
  • G V I
  • Conductance matrix voltage vector current
    vector
  • Size of matrix/vectors is extremely large
    (multi-million)
  • Through macro-modeling, get
  • I A V S,
  • Relates port currents (I)to port voltages (V)
  • A is a much smaller matrix(few thousands)
  • Abstract away the internal nodes

11
Violation Region and Sampling Nodes
  • Divide the die into small tiles
  • Hot spot (yellow) part of network with bad
    supply voltage
  • Violation region tiles covering hot spot (yellow
    orange) surrounding tiles within effective
    radius of decap (red)
  • Sampling nodes (green)nodes with worst voltage
    drop, sampled one per tile in the violation
    region
  • With macro-modeling technique, network is reduced
    to sampling nodes in the violation region All
    other nodes are abstracted away
  • If two hot spots overlap or close, they are
    merged into one violation region

Tile
12
Overall Flow
13
Non-uniform Grid
  • Definition
  • Voltage gradient (n1, n2) (V(n1)-V(n2))/distance
    (n1,n2)
  • Usually multiple violation regions in a network
  • Some regions are large with a slow voltage
    gradient
  • Need coarse grain tile to reduce problem size
  • Some regions are small with a large voltage
    gradient
  • Need fine grain tile to enable one sampling node
    to represent the entire sampling region
  • Use non-uniform grid, so that optimization
    problem size of all violation regions are within
    limitation

How large should a tile be?
14
Outline
  • Decap allocation problem
  • Prior art
  • Our solution
  • Network reduction through macro-modeling
  • Decap optimization using charged-based sequence
    of LP
  • Charge-based nodal equations
  • Charge-based decap optimization formulation
  • Sequence of LP
  • Experimental results
  • Summary

15
Charge-based Nodal Equations
  • Violation time window ts, te
  • Current-based nodal equations of a macro-model
  • I A V S, for each time point
  • I is 0 if no external elements
  • During decap optimization, using AYB0
    to approximate the
    transient analysis

16
Original Decap Allocation Problem
  • Objective Identify decap locations and minimize
    the total decap to be added
  • Constraints
  • Voltage constraints voltage at all
    transistors/gates should be better than a
    specified threshold, at all time
  • Circuit system constraints KCL, KVL and circuit
    element equations
  • Decap constraints amount of decap allowed at a
    location is limited

17
Charge-Based Voltage Constraints
  • Voltage should be ? Vthre at all time points
  • Vi,t ? Vthre , ?t ?ts,te
  • In charge-based formula,
  • Approximated to a trapezoid area Yi ?
    (Vo,iVthre) (te-ts)/2
  • ts, te is violation time window
  • Vo,I is the voltage at time ts
  • Charge-based voltage constraints in vector formY
    ? (te ts) . (Vo,1Vthre)/2, (Vo,2Vthre)/2,
    ., (Vo,iVthre)/2 T

18
Charge-based Circuit System Constraints
  • Charge released from decap during ts,te
  • Qi (Vo,i-Vi) Ci
  • Its influence on voltage (Y) is governed by
  • Q A Y B
  • Charge from decap should be large enough to pull
    the voltage above Vthre
  • (Vo,1 V1 ).C1, (Vo,2 V2 ).C2, , (V o,m-Vm
    ).Cm T ? A Y B
  • Y ? (te ts) . (Vo,1Vthre)/2,
    (Vo,2Vthre)/2, ., (Vo,iVthre)/2 T

19
Charge-based Decap Allocation
  • Minimize ? Ci
  • Subject to
  • Y ? (te ts) . (Vo,1Vthre)/2,
    (Vo,2Vthre)/2, ., (Vo,iVthre)/2 T
  • // voltage constraints
  • (Vo,1 V1 ).C1, (Vo,2 V2 ).C2, , (Vo,m-Vm
    ).Cm T ? A Y B
  • //
    circuit system constraints
  • Ci ? C max,I // decap constraints
  • Yi (Vo,iVi) (te-ts)/2
  • Circuit system constraints are non-linear
  • The objective and the other constraints are linear

20
Sequence of Linear Programming
  • In (Vo,1 V1 ).C1, (Vo,2 V2 ).C2, , (Vo,m-
    Vm).Cm T ? A Y B, voltages Vi change with
    decap to be added, Ci
  • Run iterations of LP to account for this
    non-linearity

21
Experimental Results
  • Benchmark circuits information
  • Benchmarked against a greedy method
  • Place decap uniformly across the core violation
    region
  • For each core violation region, the amount of
    decap placed is decided through binary search

Analysis CPU(s)
time points
Worst voltage(v)
Supply voltage(v)
nodes (million)
Chip
7
42
2.14
2.50
0.2
Circuit 1
345
62
1.42
1.65
4.9
Circuit 2
22
Experimental Results - Circuit 1
23
Experimental Results - Circuit 2
24
Advantages
  • Our method comes up with an accurate decap
    allocation within 1-2 transient analysis
    iterations, compared with many iterations of
    transient analysis (sensitivity calculation) of
    the previous methods
  • Our method scales very well with p/g network size
  • Our charge-based SLP optimization method obtains
    the decap budgeting through several iterations of
    linear programming and linear equations solution

25
Summary
  • Solved the decap allocation problem optimize the
    amount of decap to reduce power supply noise
  • Where to add?
  • How much to add at each location?
  • Proposed the efficient optimization methods
  • Several techniques to reduce problem size
    (macro-modeling, sampling, and consideration of
    effective radius for decap)
  • Charge-based sequence of linear programming
    optimization
  • Iterations of linear programming and linear
    equations solution

26
  • Thank You!
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