VHDL Development for ELEC7770 VLSI Project

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VHDL Development for ELEC7770 VLSI Project
Chris Erickson Graduate Student Department of
Electrical and Computer Engineering Auburn
University, Auburn, AL 36849 Chris.Erickson_at_auburn
.edu
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Objectives

• Logically perform the designed functions
• Be efficient
• Code length
• Routines
• Signal utilization
• Perform the functions appropriately per cycle

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Component Development

• All components designed developed independently
• Instruction Register
• Program Counter
• Register File
• Data Register
• Multiplexers

Test RS
A
Test RT
Register File
Test RD
B
Test RegWrite
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Multicycle Datapath

• Cycles per instruction (CPI)
• Load Word 5
• Store Word 4
• Register-type 4
• Branch 3
• Jump 3

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3 to 5 Cycles per instruction
Step R-type (4 cycles) Mem. Ref. (4 or 5 cycles) Branch type (3 cycles) J-type (3 cycles)
Instruction fetch IR ? MemoryPC PC ? PC1 IR ? MemoryPC PC ? PC1 IR ? MemoryPC PC ? PC1 IR ? MemoryPC PC ? PC1
Instruction decode/ Register fetch A ? Reg(IR25-21) B ? Reg(IR20-16) A ? Reg(IR25-21) B ? Reg(IR20-16) A ? Reg(IR25-21) B ? Reg(IR20-16) A ? Reg(IR25-21) B ? Reg(IR20-16)
Execution, Branch Jump completion ALUOut ? A op B ALUOut ? Asign extend IR15-0 If (AB) then PC?ALUOut PC?PC31-26 IR25-0
Mem. Access or R-type completion Reg(IR15-11) ? ALUOut MDR?MALUout or MALUOut?B
Memory read completion Reg(IR20-16) ? MDR
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Control FSM
Start
State 0
1
lw or sw
J
R
B
2
3
6
8
9
lw
sw
4
5
7
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Code

• Initialize, set state 0
• If state 0 thenSet state 0 signalsSet state
  1 for next clock cycle
• If state 1 thenSet state 1 signalsSet state
  2 for next clock cycle
• If state 2, depending on opcode, we will either
  go down path of register-type, load word, store
  word, branch, or jump instruction.

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Cycle Boundaries

• Multiplexers are handled at the end of each cycle
• Multiplexer outputs serve as variables to be
  used as inputs for the next clock cycle
• Either a multiplexer or another stand-alone
  component must have a steady-state output to
  serve as input for the next cycle

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Multicycle Datapath
Shift left 2
25-0
25-21
28-31
20-16
PC
Instr. reg. (IR)
A Reg.
Addr.
15-11
Memory
ALU
Register file
ALUOut Reg.
Data
Mem. Data (MDR)
B Reg.
1
Sign extend
Shift left 2
0-15
Opcode
31-25
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Completed !!

• Any Question? Comments?