Example using bridge over trouble wrappers : automated interface synthesis

1
Example using bridge over trouble wrappers
automated interface synthesis
2
Notation introduction

• When the protocol is in a state and a clock tick
  occurs, the transition whose guard evaluates to
  true is taken.
• Guards check an action is blocking if it has a
  guard.
• Presence c? (c must be 1)
• Absence c (c must be 0)
• Req! a control signal is issued
• Address!y a data signal is issued with value y
• They didnt tell what is the symble means

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Pipeline and handshake (1)
0 1 2 4 5
0 1 2 3
0 1 2 3
4
Pipeline and handshake (2)
0 1 2 3 1 2 4 5
0 1 2 3 4 2 3 5
0 1 2 3 1 2 3
5
Pipeline definition

• P (Q,S,D,V,A,-gt,q0,qf)
• Q 0,1,2,3,4,5
• S Req, Ack, Rdy
• D Address, Data
• V internal variable
• A actions
• -gt Q x A x Q state transition relation e.x.
  (0,A1,3)
• q0 0 qf 5

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Handshake definition

• P (Q,S,D,V,A,-gt,q0,qf)
• Q 0,1,2,3
• S SEL,READ,ENABLE
• D ADDR,RData
• V internal variable
• A actions
• -gt Q x A x Q
• q0 0 qf 3

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Interface definition

• Given 2 protocols
• P1 (Q1,S1,D1,V1,A1,-gt,r0,rf)
• P2 (Q2,S2,D2,V2,A2,-gt,t0,tf)
• A specification f D1 -gt D2 relating their data
  channels must be provided.
• I (Q,S,D,V,A,-gt,qo,qf)
• Q bt (Qt,Qr) where Qt bt P1, Qr bt P2
• S S1 union S2
• D D1 union D2
• V data buffers there is one buffer for each di
  and f(di)
• A set containing one action complementary to
  each of the actions in A1 and A2
• -gt relate the different states in Q as per the
  algorithm
• Q0 ltr0,t0gt is the initial control state and
  qf ltrf,tfgt is the final state
• In addition, I will have a set of counters X
  xi with one counter for each pair of data
  channels.

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step1

• A complete description of the control state of
  the interface and its counters in that state is
  written as ltR,Tgt,X
• R is a set of states from P1
• T is a set of states from P2
• X is the status of the counters
• valid(S,X) is true if, for every data write
  operation in a candidate action S, all required
  data has been read in S.

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Algorithm 1 interface synthesis

• Q empty set
• Q is the state space of I
• PendingStates r0,t0,X
• Let R,T,X be some state in the set
  pendingStates
• While pendingState ! empty do
• for all r bt R, S1 r S1-gt, t bt T, S2
  t-S2-gtdo
• S1computecomplement(S1)
• S2computecomplement(S2)
• if valid(S1US2,X) then
• Rcomputetarget(R,S1)
• Tcomputetarget(T,S2)
• Xmodifycounter(x,S1US2)
• addtransition R,T,X -gt R,T,X
• ifR,T,X nbt QUpendingStates then
• Add R,T,X to pending States
• end if
• end if
• end for
• Add R,T,X to Q and remove from pending States

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Problems about the algorithm

1. ComputeComplement(S1)input a transitionoutput
   another transitionis the function return an
   opposite arrow with the same variable on it?
2. Valid(S,X)input S, transition X,
   counteroutput true if every data required in S
   is available
3. Computetarget(source,S) return the set that
   state in S can reach via X (transition)
4. ModifyCounters(X,S)if a data is required at the
   transition, the counter is increase. If a data is
   sent, the counter is decresed.