Digital Logic Circuits Review I

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Digital Logic Circuits Review I

• Dr. Voicu Groza
• SITE Hall, Room 5017
• 562 5800 ext. 2159
• Groza_at_SITE.uOttawa.ca

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Outline

• Logic Function
• Boolean Algebra
• Logic Functions Minimization
• Logic Gates and Combinational Circuits

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Logic function

• z F(x0, x1, x2, ) z ?0, 1, xk ?0, 1, k
  0,1,2,
• F can be represented by
• logic expression
• truth table
• K-map

x0 x1 x2 x3
Logic Circuit
z
Logic Inverter
x z
z x
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• BOOLEAN ALGEBRA
• B, , , ?, 0, 1, where
• B set with at least 2 distinct elements
• 0, 1 2 constants ? B
• OR
• ? AND
• equivalence relationship, with usual
  properties
• reflexivity (? x ? B) ? (x x)
• symmetry (? x, y ? B) ? (x y ? y x)
• transitivity (? x, y, z ? B) ? (x y and y z
  ? x z)
• Parentheses are allowed

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Proof
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Proof
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DeMorgans Theorems
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Minterms
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Canonical form of logic function
Sum of Products F ABC ABC ABC ABC Sum
of minterms F S (m2, m3, m5,
m7)
F S (2, 3, 5, 7)
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Simplifying logic functions using Boolean algebra
rules
A
B
C
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Karnaugh map gt graphical representation of a
truth table of a logic function.
Each line in the truth table corresponds to a
square in the Karnaugh map.
The Karnaugh map squares are labeled so that
horizontally or vertically adjacent squares
differ only in one variable. (Each square in the
top row is considered to be adjacent to a
corresponding square in the bottom row. Each
square in the left most column is considered to
be adjacent to a corresponding square in
the right most column.)
Recommending for functions represented by
sum of minterms logic expressions
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Recommend for functions represented by sum of
minterms logic expressions
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Implicants

• Given a logic function z F(x0, x1, x2, )
• Implicant product term that,
• if equal to 1, implies f 1
• whenever the implicant is 1gt f 1
• f can be 1 other times, as well may be implied
  by other implicants, than the 1 at hand
• from the K-map point of view, an implicant is a
  rectangle of 1, 2, 4, 8, (any power of 2) 1s
• Prime Implicant cannot be totally covered by
  another implicant
• (e.g., AC, BC, AB)
• Each 1 which is covered by a single implicant
  is marked with a star ()
• Essential Prime Implicant a prime implicant
  that contains at least one 1
• A minimum cover of a logic function has to
  contain all its prime implicants

F
B
0 1 3 2
B C
0 0 1 1
4 5 7 6
0 1 1 0
A
A B C
C
A C
B
0 1 3 2
A C
0 0 1 1
4 5 7 6
0 1 1 0
A
B C
C
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The logic function can be simplified by replacing
canonical terms with a minimum cover of prime
implicants, obtained by properly combining
squares (looping) of the Karnaugh maps which
contain 1s.
A B C F (0) 0 0 0 0 (1)
0 0 1 0 (2) 0 1 0 1 (3) 0
1 1 1 (4) 1 0 0 0 (5) 1 0
1 1 (6) 1 1 0 0 (7) 1 1
1 1
B
A B
0 1 3 2
0 0 1 1
4 5 7 6
0 1 1 0
A
B C
C
A C
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Equivalent Gate Symbols
A . B
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TWO-LEVEL NAND gate implementation of the
sum-of-product logic functions
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Incompletely Specified Logic Functions
dc -gt x dont care terms
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(Set-Reset)
SET
RESET
Weird state
Set state
HOLD
Reset state
Hold state
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Characteristic (functional) table
Q(t?t) D(t)
0 0 1 1
0 1 1 1
1 0 1 0
0 1
1 0
1 1 0 1
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Connection diagram of the 7474 Dual
Positive-Edge-Triggered D Flip-Flops with
Preset and Clear.
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CHARACTERISTIC (FUNCTIONAL) TABLE
EXCITATION TABLE
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CHARACTERISTIC (FUNCTIONAL) TABLE
EXCITATION TABLE
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Synchronous 4-bit Counter
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Excitation Equations






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Implementation of 4-bit synchronous counter
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Another Synchronous 4-bit Counter
Using D flip-flops has the distinct advantage of
a straightforward definition of the flip-flop
inputs the current state of these inputs is
the next state of the counter .
The logic equations for all four flip-flop
inputs D3, D2,
D1, and D0 are
derived from this
truth
table as
functions of the
current states of the
counters
flip-flops
Q3, Q2, Q1, and Q0.
Karnaugh maps can
be used
to simplify
these equations.
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Memory Unit

• Capacity
• 2k words
• 1 word n bits

• Read operation (RD)
• Apply address to address bus (Ak-1A0)
• Apply control signal (RD) to have data appear on
  data bus (Dout)
• Read data from data bus to destination register