Extending LeonMP with Local Memory

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Extending Leon-MP with Local Memory

• Nitin Bhardwaj
• Embedded Systems Group
• Dept. Of Computer Science and Engineering
• IIT Delhi

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Presentation Outline

• Introduction
• Objective of the Project
• Details of DCache and IU Interface
• Details of Local Memory, Dcache and IU Interface
• Testing and Implementation
• Conclusion
• References

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Introduction

• Why Local Memory ?
• Efficient Utilization of On-chip Memory Space.
• Dcache interfaces with slower off-chip Memory.
• Minimize total Execution time.
• Proved that SPM has 34 lower Area and 40
  lower
• Power consumption than a cache memory of
  same capacity.

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Objective
PCI
DSU
AHB Controller
User I/O
AMBA AHB
AHB BOOT REG
AHB/APB Bridge
DSL
UART/Timers/IO Ctrl
Memory Controller
AMBA APB
IRQ CTRl1
IRQ CTRl2
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Objective
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Cache and IU Interface
Cache
ici.
iu
icache
dci.
dcache
Icache
dcache
iu
Memory
ahb
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Dcache Input Signals Dcache Output
Signals

• Eaddress, eenaddr
• Maddress, enaddr
• Asi
• Read
• Write
• Size
• Signed
• nullify
• lock
• flush

• Data
• Mexc
• Hold
• Mds
• Werr
• Icdiag
• Dsudata

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How Dcache Works
Edata
Eaddress
Maddress
address
cachemem
align

tagout
Hit
memory
WB
merge
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Timing Diagrams Cache Hit- Store Instruction
clk
1.
eenaddr
2.
enaddr
read
write
datain
hold
10
Timing Diagrams of Data Cache Access Cache Hit-
Store Instruction
clk
Execution Stage Tag is retrieved
1.
eenaddr
2.
enaddr
Memory stage Miss or Hit detect. If Miss
Stall the pipeline.
read
write
datain
hold
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Cache Miss- Store Instruction
clk
stall
1.
eenaddr
2.
enaddr
write
hold
mds
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Cache Hit- Load Instruction
clk
eenaddr
enaddr
read
hold
mds
dataout
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Cache Miss- Load Instruction
clk
eenaddr
stall
enaddr
read
hold
mds
dataout
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Local Memory,Cache and IU Interface
interface
dci.
icache
dco.
oci.
dcache
Integer unit
oco.
lmi.
lmemory
lmo.
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Timing Details of Combinational Local Memory
clk
enable
oci.enaddr
oci.enaddr and not oci.read
write
datain
dataout
Store in local memory
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Timing Details of Sequential Local Memory
clk
enable
oci.eenaddr or oci.enaddr
oci.enaddr and not oci.read
write
datain
dataout
1.) Calculate the address location 2.) Read Data
From LM depending on size,signed
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Problem in Sequential Local Memory
Solved
clk
enable
oci.eenaddr or oci.enaddr
oci.enaddr and not oci.read
write
size
10
00
datain
dataout
Pass the data to processor on the next rising
edge of clock
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Testing

• Independent Checking of LM module.
• Combined LM module with Leon.
• Taken Dcache and Icache address traces for
  setting the range of LM.
• Initialize LM from a ram.dat file.
• Checked the functioning of Local Memory for
  several address ranges, found it entering into
  error mode.
• Taken the traces of Dcache address and the
  corresponding Dcache data retrieved both in case
  of Hit and Miss .
• Match the above traces for Leon and LeonLM.
• Finally The Test Completed OK.

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Testing contd..

• LM module was purely combinational.
• Changed the LM module to respond on the clock
  edge.
• Tested the functioning of LM for several address
  ranges.
• Finally Test Completed OK.
• Changed the LM Interface to imitate the behavior
  of SRAM.
• Again did the matching of trace files from Leon
  and LeonLM.
• Checking the functioning of Local Memory for
  several address ranges
• The Test is Completed OK.

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Implementing on FPGA

• Made a UCF file to port LeonLM on Xess Board.

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References

• LEON
• http//www.gaisler.com
  http//groups.yahoo.com/group/leon_sparc/   
• SPARC  v8 http//www.sparc.com/standards/V8.pdf
• LEON synthesis onto ADM-XRC http//www.cse.iitd.e
  rnet.in/esproject/homepage/docs/seminars/anup/leon
  .ppt

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• Questions ?