CS310, Computer Architecture

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Counters and Adders

• CS310, Computer Architecture

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Review Digital Logic Gates

• Composed of one or a few transistors
• Implement Boolean functions, such as
• And
• Or
• Not
• etc.
• These, in turn, compose integrated circuits

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The AND gate
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The OR gate
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The NOT gate
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The NAND gate

• Actually, its an AND and a NOT.
• NOT is abbreviated with a circle before the
  output
• So you first take the AND, then negate it

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The NOR gate

• Analogously, an OR and a NOT

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The XOR gate

• True if inputs are different
• False if inputs are the same

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Combinational Circuits

• i.e., The majority circuit from last class
• Steps
• 1. Make a truth table
• Enumerates all possible input values
• Includes what the outputs should be
• 2. Represent the output as a sum of minterms
• 3. Construct the circuit using AND, NOR and NOT
  gates
• We can get this easily from step 2.
• Remember that you can construct any combinational
  circuit using only NAND or only NOR gates

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Example

• Make sure its nailed in
• Suppose this is our truth table (a, b, c are
  inputs, z is output)
• Design the circuit

a b c z
0 0 0 0
0 0 1 0
0 1 0 1
0 1 1 0
1 0 0 0
1 0 1 1
1 1 0 0
1 1 1 1
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Sequential Circuits

• Differ from combinational
• Output is a function of both current and previous
  inputs
• Requirement MEMORY!

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The SR Flip/Flop

• One type of memory
• SR stands for Set/Reset
• Can implement with two NAND gates or two NOR
  gates
• Idea
• You have two states Set (0 or 1) and Reset (0 or
  1)
• If Set is 1, the output is 1
• Requires Reset to be 0
• If Reset is 1, the output is 0
• Requires Set to be 0
• Way its done
• Feed the output of one NAND (NOR) gate into the
  second NAND (NOR) gate

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Implementation

• Feed the output of one NOR (NAND) gate as an
  input of the second NOR (NAND) gate
• Lets look at the truth table
• Note we have THREE inputs S, R, and old Q
• Output is the new Q, call it Q

Called a bistable device.
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Reset of a Flip/Flop Stage 1

• The initial inputs are both 0. State of the
  flip-flop is set (well assume it has been set
  and returned to inactive state), so here Q1, R0
  and S0).

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Reset of a Flip-Flop Stage 2

• Apply a 1 to input R.
• Output of top NOR goes to 0 (1 NOR 0 0) -gt Q
• Q is input into bottom NOR, produces 1 (0 NOR
  S0) -gt (not Q)

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Reset of a Flip/Flop Stage 3

• Reset R to 0.
• Output of top NOR is still 0 because of NOT Q (0
  NOR 1) -gt Q
• This in turn, implies Q and NOT Q do not change

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Weve also shown SET works

• Although we may not have known it
• But since flip-flops are symmetric.
• Simply switch S and R above, and also Q and (not
  Q)
• Then weve proven set.

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Clocked Flip/Flops

• SR flip/flops by themselves are not used in
  computers
• Because computers require synchrony with a clock
• Clocked flip/flops are, however
• The extra AND gates make sure that the state of
  outputs (Q, not Q) can only change on clock cyles
  (clock1)

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SR Flip/Flop Boolean Expression

• Form a truth table
• Make the Karnaugh Map
• Obtain the arithmetic expression

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Types of clocked SR flip/flops

• Level Triggered
• Active High State can change when clock1
• What we just saw
• Active Low State can change when clock0
• Can just add a NOT gate
• Edge Triggered
• Leading Edge State can change when clock goes
  from 0 to 1
• Trailing Edge State can change when clock goes
  from 1 to 0
• In time critical systems, which is better (level
  or edge)?

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Clocked D Flip/Flop

• Simplifies things a bit
• Uses a single input data (1RESET, 0SET)

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Master/Slave Flip/Flop

• Used for shifting bits
• When clock1, the state of the master flip-flop
  changes
• When clock0, this output is moved to the slave
  flip-flop

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JK Flip/Flop

• Used for bit toggling
• Two inputs, J and K. If theyre both zero, keep
  the same state and if theyre both one, toggle.
  Otherwise the output is just J

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JK Flip/Flop Boolean Expression

• Truth table
• Karnaugh Map
• Boolean Expression

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Designing a Counter

• Using Flip/Flops (sequential) and some
  combinational
• Storing the current number in the counter
• We can view each flip/flop as holding a binary
  digit
• In each clock cycle, the state of each flip/flop
  changes to the state for the next count number
• Incrementing the counter
• We pass the outputs of each flip/flop into a
  combinational circuit and feed them back as
  flip/flop inputs
• Repeat

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Schematically
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Counter from 0 to 7

• Reminder of the binary values
• Each flip/flop holds a digit (Q)

Count Q1 Q2 Q3
0 0 0 0
1 0 0 1
2 0 1 0
3 0 1 1
4 1 0 0
5 1 0 1
6 1 1 0
7 1 1 1
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Populating this table

• We need to determine the J and K values for each
  flip/flop
• Dont care (X) is perfectly acceptable
• Thus we must ask ourselves
• For each flip/flop, do we need to toggle? Or
  reset?

Q1 Q2 Q3 J1 K1 J2 K2 J3 K3
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
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Combinational Circuitry

• Obtain a sum of minterms for each of the J/K
  values
• Make dont cares 0 or 1 to simplify the
  explanation
• Design the combinational circuitry using the sum
  of minterms note we have both Q and NOT Q for
  each flip/flop

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Decoder

• Used to select a resource based on a binary
  number
• Also called a selector
• An n-input decoder can choose between 2n devices
• Only one active at a given time

a b c o0 o1 o2 o3 o4 o5 o6 o7
0 0 0 1 0 0 0 0 0 0 0
0 0 1 0 1 0 0 0 0 0 0
0 1 0 0 0 1 0 0 0 0 0
0 1 1 0 0 0 1 0 0 0 0
1 0 0 0 0 0 0 1 0 0 0
1 0 1 0 0 0 0 0 1 0 0
1 1 0 0 0 0 0 0 0 1 0
1 1 1 0 0 0 0 0 0 0 1
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Decoder Circuitry
a b c o0 o1 o2 o3 o4 o5 o6 o7
0 0 0 1 0 0 0 0 0 0 0
0 0 1 0 1 0 0 0 0 0 0
0 1 0 0 0 1 0 0 0 0 0
0 1 1 0 0 0 1 0 0 0 0
1 0 0 0 0 0 0 1 0 0 0
1 0 1 0 0 0 0 0 1 0 0
1 1 0 0 0 0 0 0 0 1 0
1 1 1 0 0 0 0 0 0 0 1
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Encoder (the reverse)
a b c d e f g h o0 o1 o2
1 0 0 0 0 0 0 0 0 0 0
0 1 0 0 0 0 0 0 0 0 1
0 0 1 0 0 0 0 0 0 1 0
0 0 0 1 0 0 0 0 0 1 1
0 0 0 0 1 0 0 0 1 0 0
0 0 0 0 0 1 0 0 1 0 1
0 0 0 0 0 0 1 0 1 1 0
0 0 0 0 0 0 0 1 1 1 1
Note With encoder inputs, there are eight but
only a subset of possible input combinations are
included in the truth table. This is because
only one can be active at a time.
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Using Encoders

• Here we show an 8-to-3 encoder
• Encoders are used to
• Identify a particular resource
• Determine the type of interrupt
• Notes
• If you connect the output of an encoder to the
  input of a decoder, you get the encoder input
  back
• Same thing if the decoder and encoder are reversed

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The Multiplexor (MUX)

• Choose an output based on a set of selector
  control values

Selector Output ----------- --------- 000 Input
0 001 Input 1 010 Input 2 011 Input
3 100 Input 4 101 Input 5 110 Input
6 111 Input 7
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The DeMultiplexor (DEMUX)

• Does the opposite choose what output to send
  the input to based on the selector values
• MUXes are much more common