A HW/SW Co-Simulator for System Validation

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A HW/SW Co-Simulator for System Validation --
ECE649 Course Project Proposal Weiwen
Zhu Dept. ECE McGill University
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• Motivation and Background
• More functionality in software
• Low power, high denisity, easy to upgrade
• HW/SW co-simulator environment
• Functionality and timing
• Speed and cost
• Ptolemy for UCB
• Hybrid modeling and simulating environment
• Component based
• Simulation for Validation

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• Objective
• Fast simulation of the HW/SW system
• Apply design pattern for software design
• Reactive software
• User interface
• Communication protocol
• Hardware resource sharing
• Multiple processors
• Buffer

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• Software Structure
• Implememt as an extension to existing Ptolemy
  domain
• Dynamic task tree
• Parameterize hardware

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• Using OO design pattern
• Reactor pattern for message dispatch
• Subscriber pattern
• Non-blocking buffering pattern

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• Simulation for Testing
• Simulation for Verification
• find constrains
• Simulation for Validation
• Pass / Fail criteria
• Simulation for Synthesis
• Find the best solution under the timing
  constrains