CSCI 330 Computer Architecture

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CSCI 330Computer Architecture

• Spring, 2009
• Doug L Hoffman, PhD

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Course Overview

• When 1210-100, MWF.
• Where McRey 317.
• Who Doug L. Hoffman
• Office Hours By appointment.
• Website http//www.dlhoffman.com/classnotes
• Syllabus will be available on the site soon.

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Course description

• This course covers advanced concepts and
  principles of computer architecture and design.
• It will start by examining the changing face of
  computer architecture and the task of the
  computer designer.

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Course description

• Quantitative principles of computer design will
  be applied to the evaluation of performance and
  reliability.

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Course description

• Topics covered include Exploitation of
  Instruction Level Parallelism in modern
  processors, including the hazards of instruction
  scheduling and the limits of ILP and advanced
  techniques for exploiting ILP.

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Course description

• Also support for thread-level parallelism
  multiprocessors and thread-level parallelism
  memory hierarchy design, including cache
  optimization and advanced topics in storage
  systems.
• Topics will be illustrated using case studies of
  actual processor designs.

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Course Grading

• Home work 40
• 10 weekly assignments.
• Tests 50
• 2 Quizzes 10 of testing total.
• Mid-Term 30.
• Final 50.
• Class participation 10

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The Text

• Computer Architecture A Quantitative Approach,
• John L. Hennessy and David A. Patterson.

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What is Computer Architecture?
CSCI 330 Computer Architecture
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Traditional Definition

• Computer Architecture is the interface between
  software and hardware. It is what a programmer
  sees.

Hennessy and Patterson have changed their minds
on this!
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Moores Law

• Gordon Moore (co-founder
• of Intel) predicted in 1965
• that the transistor density of
• semiconductor chips would
• double roughly every
• 18 months.

Not a prediction of performance growth!
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Crossroads Uniprocessor Performance
From Hennessy and Patterson, Computer
Architecture A Quantitative Approach, 4th
edition, October, 2006

• VAX 25/year 1978 to 1986
• RISC x86 52/year 1986 to 2002
• RISC x86 ??/year 2002 to present

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Changing Conventional Wisdom

• Old Conventional Wisdom Power is free,
  Transistors expensive
• New Conventional Wisdom Power wall Power is
  expensive, (Can put more on chip than can afford
  to turn on)
• Old CW Sufficiently increasing Instruction Level
  Parallelism via compilers, innovation
  (Out-of-order, speculation, VLIW, )
• New CW ILP wall law of diminishing returns on
  more HW for ILP
• Old CW Multiplies are slow, Memory access is
  fast
• New CW Memory wall Memory slow, multiplies
  fast (200 clock cycles to DRAM memory, 4 clocks
  for multiply)
• Old CW Uniprocessor performance 2X / 1.5 yrs
• New CW Power Wall ILP Wall Memory Wall
  Brick Wall
• Uniprocessor performance now 2X / 5(?) yrs
• ? Sea change in chip design multiple cores
  (2X processors per chip / 2 years)
• More simpler processors are more power efficient

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Sea Change in Chip Design

• Intel 4004 (1971) 4-bit processor,2312
  transistors, 0.4 MHz, 10 micron PMOS, 11 mm2
  chip

• RISC II (1983) 32-bit, 5 stage pipeline, 40,760
  transistors, 3 MHz, 3 micron NMOS, 60 mm2 chip

• 125 mm2 chip, 0.065 micron CMOS 2312 RISC
  IIFPUIcacheDcache
• RISC II shrinks to 0.02 mm2 at 65 nm
• Caches via DRAM or 1 transistor SRAM?
• Proximity Communication via capacitive coupling
  at gt 1 TB/s ?(Ivan Sutherland _at_ Sun / Berkeley)

• Is the Processor the new transistor?

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Déjà vu all over again?

• Multiprocessors imminent in 1970s, 80s, 90s,
• todays processors are nearing an impasse as
  technologies approach the speed of light..
• David Mitchell, The Transputer The Time Is Now
  (1989)
• Transputer was premature ? Custom
  multiprocessors strove to lead uniprocessors?
  Procrastination rewarded 2X seq. perf. / 1.5
  years
• We are dedicating all of our future product
  development to multicore designs. This is a
  sea change in computing
• Paul Otellini, President, Intel (2004)
• Difference is all microprocessor companies switch
  to multiprocessors (AMD, Intel, IBM, Sun all new
  Apples 2 CPUs) ? Procrastination penalized 2X
  sequential perf. / 5 yrs? Biggest programming
  challenge 1 to 2 CPUs

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The Gurus Say

• "The move from sequential to parallel
  computing that is now underway will be as
  profound a change for the IT industry as the move
  to the web in the 1990s or the move to personal
  computers and workstations in the 1980s."
• - Bill McColl,
• Professor of Computer Science at
• Oxford University, Founder and
• CEO of Parallel Machines, Inc.
• "Ultimately, the advice I'll offer is
  that...developers should start thinking about
  tens, hundreds, and thousands of cores now."
• - Anwar Ghuloum,
• Principal Engineer,
• Intel's Microprocessor Technology Lab
• "As large-scale, highly parallel
  computingcloud computingbecomes the industry
  standard, the next generation of software
  developers will need to move towards a model
  based on hundreds or thousands of computers
  working together."
• - Andrew Pederson
• Google Spokesman

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Parallelism By Necessity

• This shift toward increasing parallelism is not
  a
• triumphant stride forward based on breakthroughs
• in novel software and architectures for
  parallelism
• instead, this plunge into parallelism is
  actually a
• retreat from even greater challenges that thwart
• efficient silicon implementation of traditional
• uniprocessor architectures.

Kurt Keutzer, Berkeley View, December 2006
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Problems with Sea Change

• Algorithms, Programming Languages, Compilers,
  Operating Systems, Architectures, Libraries,
  not ready to supply Thread Level Parallelism or
  Data Level Parallelism for 1000 CPUs / chip,
• Architectures not ready for 1000 CPUs / chip
• Unlike Instruction Level Parallelism, cannot be
  solved by just by computer architects and
  compiler writers alone, but also cannot be solved
  without participation of computer architects
• This course (and 4th Edition of textbook Computer
  Architecture A Quantitative Approach) explores
  the shift from Instruction Level Parallelism
  (ILP) to Thread Level Parallelism (TLP) / Data
  Level Parallelism.

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The Ultimate Destination

• The Data Center is the Computer
• - David Patterson

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Next Time

• The Changing Face of
• Computer Architecture

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Questions or Comments?