3' Decision Diagrams

1
3. Decision Diagrams

• Introduction
• Theory Boolean differential algebra
• Theory Decision diagrams
• Fault modelling
• Test generation
• Fault simulation
• Fault diagnosis
• Testability measuring
• Design for testability
• Built in Self-Test

2
Basics of Theory for Test and Diagnostics
Two basic tasks 1. Which test patterns are
needed to detect a fault (or all faults) 2.
Which faults are detected by a given test (or by
all tests)
System
Boolean differential algebra
Gate
0
1


0
0
1
DD
Decision diagrams
Multiplier
BDD
3
Overview Decision Diagrams

• Binary Decision Diagrams (BDDs)
• Structurally Synthesized BDDs (SSBDDs)
• High Level Decision Diagrams (DD)
• DDs for Finite State Machines
• DDs for Digital Systems
• Vector DDs
• DDs for microprocessors
• DD synthesis from behavioral descriptions
• Example of DD synthesis from VHDL description

4
Binary Decision Diagrams
Functional BDD
Simulation
0 1 1 0 1 0 0
Boolean derivative
5
Fault Propagation Problem
Logic gate
Logic circuit
6
Fault Propagation with BDD
1
y
y
x
x
1
1
1
1
0
1
x
x
x
x
2
3
2
3
x
x
x
x
4
5
4
5
0
x
x
x
x
6
7
6
7
0
0
0
7
Test Generation with SSBDDs
x11?0
Test generation for
1
1
x11
1?0
x21
1
x11
y
x1
x21
1

x2
1?0
1?0
x12
x31
x4
x12
1?0
x31
0
0
x3
y

1
0
x4
0
x22
x32
x13

x13

x22
x32
0
8
Test Generation for Multiple Faults
Testing multiple faults by groups of patterns
Multiple fault x1?1, x2?0, x3?1
An example where the method of test pairs
does not help
Fault masking
Fault detecting
T1
T2
T3
x3?1
x1?1
x2?0
9
Test Generation for Multiple Faults
Method of test pattern groups on DDs
D
D
D
x1
x2
x1
y
D

x2
D
Test group for testing a part of circuit
D
0
0
x3
x3
x4
x1
y

1
0
x4
0

x2
x3
x1

Disjunctive normal forms are trending to
explode DDs provide an alternative
Multiple fault x1?1, x2?0, x3?1
10
Synthesis of BDDs
Functional synthesis BDDs
Shannons Theorem
Example
Using the Theorem for BDD synthesis
x1
y
x2
xk
y
x3
x3
x4
x4
11
BDDs for Logic Gates
Elementary BDDs
AND
x1
x1
x2
x1
x2
x3
y

x2
y
x3

Adder
x3
x1
OR
x2
x1
y
1
x1
y
x2
x3
x3
x2
x2
x3
x3
NOR
x1
x2
y
x1
x2
x3
1
x3
12
BDDs for Flip-Flops
Elementary BDDs
S
D Flip-Flop
J
JK Flip-Flop
q
c
D
q
D
C
S
C
K
q
c
q
R
K
R
RS Flip-Flop
q
J
q
c
S
S
R
C
q
q
U
R
R
U - unknown value
13
Synthesis of SSBDD for a Circuit
Structurally Synthesized BDDs
DD-library
y
a
b
Given circuit
x1
x1
x22
a
a
b
x21
1
x2
y
x21
x3

x22
1
SSBDD
x3
Superposition of DDs ?
b
y
x22
x22
a
y
x1
Compare to
x3
x3
Superposition of Boolean functions
x21
b
a
14
Logic Circuits and SSBDDs
Structurally synthesized BDD for a subcircuit
(macro)
To each node of the SSBDD a signal path in the
circuit corresponds
y cyey cy ? ey x6,e,yx73,e,y ? deybey y
x6x73 ? ( x1 ? x2 x71) ( x5? x72)
15
Structurally Synthesized SSBDDs
16
BDDs and High-Level DDs
Test generation at logic level (BDD)
Test generation at higher levels (DD)
17
Data Path in Digital Systems
Control Path
y
x
Data Path
18
Data Path High-Level DD Synthesis
Control Path
y
x
Data Path

19
Data Path HLDD Synthesis
Control Path
y
x
Data Path
20
Data Path HLDD Synthesis

21
High-Level Decision Diagrams
Superposition of High-Level DDs A single DD for
a subcircuit
Instead of simulating all the components in the
circuit, only a single path in the DD should be
traced
22
Control Path in Digital Systems
State Transition Diagram
Control Path (Finite state machine)
Combinational circuit
y
x
Next state
q
q
State
Output
Res
Memory register
q/y
State
23
High-Level DDs for Finite State Machines
State Transition Diagram
High level vector DD
Res
1/0
x1
3/0
2/1
x2
5/0
4/1
x1
6/1
DD computes the value of the vector (q,y)
24
Control Path in Digital Systems
Low-Level Control Path (Control Logic for a
single Flip-Flop)
High-Level Control Path (Finite State Machine)
Combinational circuit
y
Combinational circuit
x1
y
x
x2
D3F(x,q)
D3
Next state
q
q
State
T1
T2
T3
Res
Memory register
25
Control Path in Digital Systems
Low-Level Control Path Control Logic for a single
Flip-Flop
26
FSM and its Binary Decision Diagram
Low-Level Control Path Control Logic for a single
Flip-Flop
SSBDD
27
HLDDs vs BDDs for FSM
SSBDD for D3
DD for the whole Control Part
2
1
3
D3
5
4
6
x1
Control Part
9
8
7
10
x2
12
13
T3
T2
x1
11
28
System of High-Level DDs
Register-Level Data Path
29
High-Level Extended Decision Diagrams
Representing transparency functions in Decision
Diagrams
30
Digital System and Data Flow Diagram
Data-Flow Diagram
Digital system
31
Synthesis of High-Level DDs
High-Level DDs can be synthesized by symbolic
execution of the Data-Flow Diagram
Data-Flow Diagram
32
Synthesis of High-Level DDs
High-Level DDs can be synthesized by symbolic
execution of the Data-Flow Diagram
Decision Diagrams
AC
AX
PC
33
Synthesis of High-Level DDs
Data Flow Diagram
Results of symbolic simulation
q 0
Begin
q 1
A B C
1
0
x
A
q 2
q 4
?
A
A 1
B B C
1
0
0
1
x
x
A
B
q 3
?
B
?
B
C
?
C
C
C
0
0
1
1
x
x
C
C
?
A A
?
B C
A
C B
C A B
q 5
END
34
Synthesis of High-Level DDs
Extraction of the behaviour for A
Results of symbolic simulation
Predicate equation for A
A (q0)(BC) ? (q1)(xA0) (?A 1)
? (q3)(xC1)( ?CB) ? (q4)(xA0)(xC0)(A ?B
C 1)
35
Synthesis of High-Level DDs
Extraction of the behaviour for A
Decision diagram for A
Predicate equation for A
A (q0)(BC) ? (q1)(xA0) (?A 1)
? (q3)(xC1)( ?CB) ? (q4)(xA0)(xC0)(A ?B
C 1)
36
High-Level DDs for Digital Systems
Data Flow Diagram
Decision Diagrams
37
High-Level DDs for Digital Systems
Decision Diagrams
Digital system
38
High-Level Vector Decision Diagrams
A system of 4 DDs
Vector DD
0
A
0
0
C
q

B C
MA.B.C.q
i

q
x
A B


q
B
C
A
i
B
q
1
1
0
5
x
?

A
1
A
1
0
A
1
C
x
?
A 1
3
i
1
A
?
i
C
q
x
?


q
C
B
C
4
3
4
0
0
1
B
x
x



A
B
C
C
A
B C
0
A
0
i
q
x
x
A BC
i
C
A
1
1
2
B
2
x



q
B

C
B
?
A
B
q
4
0
5
3
0
C
0
x
?

B
A B
q

x
q

A
1
i
B
C
q
?
i
B
2
0
1
0
5
q
x
x


q


4
A
B
C
B
A
5
1
A
1
?
B
C
1
3
i
0
1
C
q

x
2
?
i
C
C
5
q
4
0
2
1
4
5
x

5
x
B
?

C
A
1
3,4

3
39
Decision Diagrams for Microprocessors
High-Level DDs for a microprocessor (example)
DD-model of the microprocessor
Instruction set
1,6
I
IN
A
3

• I1 MVI A,D A ? IN
• I2 MOV R,A R ? A
• I3 MOV M,R OUT ? R
• I4 MOV M,A OUT ? A
• I5 MOV R,M R ? IN
• I6 MOV A,M A ? IN
• I7 ADD R A ? A R
• I8 ORA R A ? A ? R
• I9 ANA R A ? A ? R
• I10 CMA A,D A ? ? A

2,3,4,5
I
R
OUT
A
4
7
A R
A
8
2
A ? R
I
A
R
9
A ? R
5
IN
10
? A
1,3,4,6-10
R
40
Decision Diagrams for Microprocessors
High-Level DD-based structure of the
microprocessor (example)
DD-model of the microprocessor
1,6
I
IN
A
IN
3
R
2,3,4,5
I
R
OUT
A
4
7
A R
I
A
OUT
8
2
A ? R
I
A
R
9
A ? R
5
A
IN
10
? A
1,3,4,6-10
R
41
Vector DDs for Miocroprocessors
DDs for representing microprocessor output
behaviour
42
DD Synthesis from Behavioral Descriptions

• BEGIN
• Memory state M
• Processor state PC, AC, AX
• Internal state TMP
• Instruction format IR OP. A. F0. F1. F2.
• Execution process EXEC
• BEGIN
• DECODE OP ? (
• 0 AC? AC M?A?
• 1 MA? AC, AC ? 0
• 2 MA? MA 1,
• IF MA 0 THEN PC ? PC
  1
• 3 PC ? A
• ......................................
• 7 IF F0 THEN AC ? AC 1
• IF F1 THEN IF AC 0 THEN PC ?
  PC 1
• IF F2 THEN (TMP ? AC, AC ? AX, AX
  ? TM)
• END
• END

Procedural description of a microprocessor
43
DD Synthesis from Behavioral Descriptions
Symbolic execution tree
Start
OP7
OP0
...
F01
1
OP3
F00
AC AC 1
AC AC M A
OP1
PC A
F11
F10
2
OP2
AC?0
5
AC0
M A AC, AC 0
F20
PC PC 1
F20
6
F20
F21
F21
11
M A M A 1
F21
9
MA0
3
AC AX, AX AC
MA1
AC AX, AX AC
PC PC 1
7
AC AX, AX AC
10
4
8
44
DD Synthesis from Behavioral Descriptions
Generation of nonprocedural descriptions via
symbolic execution Terminal contexts
45
DD Synthesis from Behavioral Descriptions
Decision Diagram for AC
0
ACM A
OP
AC
1
0
2,3
AC
7
0
0
F0
F2
1
1
AX
0
AC1
F2
1
46
DD Synthesis from VHDL Descriptions
VHDL description of 4 processes which represent
a simple control unit
47
DD Synthesis from VHDL Descriptions
DDs for state, enable_in and nstate
1
rst
state
1
0
1
nstate
clk?
0
Superposition of DDs
state
1
0
state
nstate
enable_in
1
1
2
0
rb0
2
1
1
clk
enable
enable_in
0
enable
48
DD Synthesis from VHDL Descriptions
DDs for the total VHDL model
49
DD Synthesis from VHDL Descriptions
Simulation and Fault Tracing on the DDs
Simulated vector
50
Hierarchical Modelling on DDs
System High-level decision diagram
1
C
A small part is simulated at the lower level
x1
1
0
x3
x2
MA.B.C.q
0
A
0
C

q
B C
i
x5
x4
x
A B
q
i
B
q
1
5
1
0
A
1
C
x6
x7
x
?
A 1
i
A
?
i
C
q
q
4
3
Component Binary Decision Diagram
1
B
0
B C
0
A
0
i
q
x
x
A BC
i
C
A
2
B
2
?
B
A small part is simulated at the higher level
to increase the speed of analysis
q
5
3
0
C
A B
x
i
B
C
Cause-effect analysis well formalized
q
?
i
B
5
q
5
1
A
?
B
C
i
1
C
q
?
i
C
5
q
4
5