N'K' Srinathsrinath_nkyahoo'com 1 RVCE

1

Compilers

• Code Generation
• MACHINE - DEPENDENT CODE
  OPTIMIZATION
• Machine Independent Compiler Features
• MACHINE - INDEPENDENT CODE
• OPTIMIZATION

N.K. Srinath srinath_nk_at_yahoo.com 1
RVCE
2

• MACHINE - DEPENDENT CODE
• OPTIMIZATION
• There are several different possibilities for
  performing machine-dependent code optimization .
• Assignment and use of registers
• Registers are used as instruction operand.
• The number of registers available is limited.
• Registers may be used to hold constants, the
  values of variables, intermediate results and so
  on.
• Registers may also be used for having address.

N.K. Srinath srinath_nk_at_yahoo.com 2
RVCE
3

• Required to find the least used register
  to replace with new values when
  needed.
• Which register to be used? The least used
  register could be replaced when there are no
  availability of registers.
• Usually the existence of jump instructions
  creates difficulty in keeping track of registers
  contents.
• Divide the problem into basic blocks to tackle
  such problems.
• A basic block is a sequence of quadruples with
  one entry point, which is at the beginning of the
  block, one exit point, which is at the end of the
  block, and no jumps within the blocks.

N.K. Srinath srinath_nk_at_yahoo.com 3
RVCE
4

CALL operation is usually considered
to begin a new basic block.

• When control passes from one block to
  another, all values currently held in registers
  are saved in temporary variables.
• For example 3, the quadruples can be divided into
  five blocks. They are
• Block -- A Quadruples 1 - 3
• Block -- B Quadruples 4

N.K. Srinath srinath_nk_at_yahoo.com 4
RVCE
5

Block -- C Quadruples 5 - 14 Block --
D Quadruples 15 - 20 Block -- E Quadruples
21 - 23
Fig. shows the basic blocks of the flow group for
the quadruples. An arrow from one block to
another indicates that control can pass directly
from one quadruple to another.
This kind of representation is called a flow
group.
N.K. Srinath srinath_nk_at_yahoo.com 5
RVCE
6

• Considering a part of the code and
  Rearranging quadruples before
• machine code generation
• Example 1) DIV SUMSQ 100 i1
• 2) MEAN MEAN i2
• 3) - i1 i2 i3
• 4) i3 VARIANCE

N.K. Srinath srinath_nk_at_yahoo.com 6
RVCE
7

LDA SUMSQ DIV 100 STA i1 LDA MEAN
MUL MEAN STA i2 LDA i1 SUB i2 STA i3 STA
Variance
shows a typical generation of machine code from
the quadruples using only a single register ie
Accumulator
N.K. Srinath srinath_nk_at_yahoo.com 7
RVCE
8

The optimizing compiler could
rearrange the quadruples so that
the second operand of
the subtraction is computed first. This results
in reducing two memory accesses.
MEAN MEAN i2 DIV SUMSQ
100 i1 - i1 i2
i3 i3 VARIANCE
N.K. Srinath srinath_nk_at_yahoo.com 8
RVCE
9

LDA MEAN MUL MEAN STA i1 LDA SUMSQ
DIV 100 SUB i1 STA VARIANCE
N.K. Srinath srinath_nk_at_yahoo.com 9
RVCE
10

• Characteristics and Instructions
• of Target Machine
• Special loop - control instructions or
  addressing modes can be used to create more
  efficient object code.
• High-level machine instructions can perform
  complicated functions such as calling procedure
  and manipulating data structures in a single
  operation.
• If multiple functional blocks can be used, the
  source code can be rearranged to use all the
  blocks or most of the blocks concurrently. This
  is possible if the result of one block does not
  depend on the result of the other.

N.K. Srinath srinath_nk_at_yahoo.com 10
RVCE
11

• MACHINE - DEPENDENT
• CODE OPTIMIZATION
•  There are several different possibilities for
  performing machine-dependent code optimization .
• Assignment and use of registers
• Divide the problem into basic blocks.
• Rearrangement of machine instruction to
  improve efficiency of execution

N.K. Srinath srinath_nk_at_yahoo.com 11
RVCE
12

• Register Allocation
• Assign specific CPU registers for specific
  values.
• Code Generation must maintain information on
  which registers
• Are used for which purposes
• Are available for reuse
• Main objective
• ? Maximize the utilization of the CPU
  registers
• ? Minimize references to memory locations

N.K. Srinath srinath_nk_at_yahoo.com 12
RVCE
13

Possible uses for CPU registers Values
used many times in a program Values that are
computationally expensive Importance ?
Efficiency ? Speed
N.K. Srinath srinath_nk_at_yahoo.com 13
RVCE
14

Register Allocation Algorithm
Register Allocation Algorithm determines how many
registers will be needed to evaluate an
expression. It also determines the Sequence in
which sub-expressions should be evaluated to
minimize register use.
N.K. Srinath srinath_nk_at_yahoo.com 14
RVCE
15

• Construct a tree starting at the
  bottom nodes
• Assign each leaf node a weight of
• ? 1 if it is the left child
• ? 0 is it is the right child
• The weight of each parent node will be computed
  by the weights of the 2 children as follows
• ? If the 2 children have different weights, take
  the max.
• ? If the weights are the same, the parents
  weight is w

The number of CPU registers is determined by the
highest summed weight at any stage in the tree.
N.K. Srinath srinath_nk_at_yahoo.com 15
RVCE
16

Example - For the following statement program
segment, determine a smart register allocation
scheme AB (CD) (EF)
N.K. Srinath srinath_nk_at_yahoo.com 16
RVCE
17

• Machine Independent Compiler
• Features
• Machine independent compilers describe the
  method for handling structured variables such as
  arrays.
• Problems involved in compiling a
  block-structured language indicate some possible
  solution.

N.K. Srinath srinath_nk_at_yahoo.com 17
RVCE
18

• STRUCTURED VARIABLES
• Structured variables discussed here are arrays,
  records, strings and sets.
• Arrays In Pascal array declaration
• Single dimension array
• A ARRAY 1 . . 10 OF INTEGER
• If each integer variable occupies one word of
  memory, then we require 10 words of memory to
  store this array.

N.K. Srinath srinath_nk_at_yahoo.com 18
RVCE
19

In general an array declaration is ARRAY
i .. u OF INTEGER Memory word allocated ( u
- i 1) words.
(ii) Two dimension array BARRAY
0 .. 3, 1 . . 3 OF INTEGER In this type of
declaration total word memory required is 0 to 3
4 1 to 3 3 4 x 3 12 word memory
locations.
N.K. Srinath srinath_nk_at_yahoo.com 18
RVCE
20

• In general
• ARRAY l1 .. u1, l2 . . u2. OF INTEGER
• Requires ( u1 - l1 1) ( u2 - l2 1)
  Memory words
• The data is stored in memory in two different
  ways.
• They are row-major and
• Column major.
• All array elements that have the same value of
  the first subscript are stored in contiguous
  locations. This is called row-major order. It is
  shown in fig.

N.K. Srinath srinath_nk_at_yahoo.com 20
RVCE
21

N.K. Srinath srinath_nk_at_yahoo.com 21
RVCE
22

Element reference To refer to an element, we
must calculate the address of the referenced
element relative to the base address of the
array.

• Compiler would generate code to place the
  relative address in an index register.
• Index addressing mode is made easier to access
  the desired array element.

N.K. Srinath srinath_nk_at_yahoo.com 22
RVCE
23

One Dimensional Array On a SIC machine to
access one dimensional array the address is
calculated by
(starting address of data) (size of each data)
(number of preceding data). Example Address
for the element A6 is Assuming the
starting address is 1000H Size of each data
is 3 bytes on SIC machine Number of preceding
data is 5 Therefore the address for A 6 is
1000 3 5 1015.
N.K. Srinath srinath_nk_at_yahoo.com 23
RVCE
24

In general for A ARRAYl..u of integer, if each
array element occupies W bytes of storage and if
the value of the subscript is S, then the
relative address of the referred element AS is
given by W(S-l).
How do you represent A5 in quadruple? A Array
1. . 100 of integer This is the declaration
of array AI 5 This is
assignment statement
N.K. Srinath srinath_nk_at_yahoo.com 24
RVCE
25

Quadruple representation Note Here if we
want to assign A3 5, then I 3 (
I is taken as 3 because we want A3). i1 I
1 ( i.e 3-12 this is because the count is
from 0) I2 i1 3 ( This is the location
where the data is to be stored.)
- I 1 i1 i1 I - 1
i1 3 i2 i2 i1 3 5 Ai2
Ai2 5
N.K. Srinath srinath_nk_at_yahoo.com 25
RVCE
26

Multi-Dimensional Array In multi-dimensional
array we assume row major order.

• How do we access an element B 2,3 of the
  matrix B 6, 4 ?
• We must skip over two complete rows before
  arriving at the beginning of row 2.
• Each row contains 6 elements so we have to skip 6
  x 2 12 array elements before we come to the
  beginning of row 2 to arrive at B 2, 3 .

N.K. Srinath srinath_nk_at_yahoo.com 26
RVCE
27

• Skipping over the first two elements of row 2
  results in arriving at at B 2, 3 .
• This makes a total of 12 2 14 elements
  between the beginning of the array and element
  B2, 3 .
• If each element occurs 3 byte as in SIC, the B2,
  3 is located relating at 14 x 3 42 address
  within the array.
• Generally the two dimensional array can be
  written as B ARRAY l1 . . . u1, l1 . . .
  u1, OF INTEGER

N.K. Srinath srinath_nk_at_yahoo.com 27
RVCE
28

How do you represent in quadruples to assign 25
to an two dimensional array? Let the array be B
ARRAY 0..3, 1..6 OF INTEGER BI, J 25
I 6 i1 - j 1 i2 i1 i2 i3 i3
3 i4 25 B i4
N.K. Srinath srinath_nk_at_yahoo.com 28
RVCE
29

Compilers

• Code Generation
• MACHINE - DEPENDENT CODE
  OPTIMIZATION
• Machine Independent Compiler Features
• MACHINE - INDEPENDENT CODE
• OPTIMIZATION

N.K. Srinath srinath_nk_at_yahoo.com 1
RVCE