Title: Anaconda Vision Processor
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2Anaconda Vision Processor
- Agenda
- Overview
- Typical applications
- Development on the Anaconda
- Q A
3Anaconda Vision Processor
- Main Features
- Camera Link Acquisition plus image processing in
1 PCI-X slot - Versatile processing module to match customer
performance/price target - Flexible and easy to deploy
4Anaconda Vision Processor-Data Flow
Data Sync
Acquisition
Image Formatter
Defect Correction
To Host
On-board Memory
Image Processing
Optional
5Anaconda Vision Processor
Acquisition
Image Formatter
Defect Correction
- Acquisition Block
- Full Camera Link or Dual Base
- Support Area-scan and Line scan cameras(Shaft
encoder, Frame trigger, etc) - Include Trigger-to-Image reliability features
On-board Memory
Image Processing
6Anaconda Vision Processor
Acquisition
Image Formatter
Defect Correction
- Image Formatter Block
- Support all current sensor architecture
- Multi-Taps, Multi-Channels
- Segmented, alternated
- Reverse Scanning direction (Horizontal and
vertical) - Tri-linear color sensors,etc
On-board Memory
Image Processing
7Anaconda Vision Processor
Acquisition
Image Formatter
Defect Correction
- Defect Correction Block
- iLUT 4 Taps of 10 to 10-bits, 8 Taps of 8 to 8
bits - FLC(Line scan), FFC (area-scan)
- Gain x Pixel Value Offset for each pixel
location in the image. Gain is between 1 and 2 - FPN Fixed-Pattern noise to correct pixel that
cant be corrected by FFC-FLC (Gain larger than
2) - CMOS sensor with Dead or Hot pixels.
On-board Memory
Image Processing
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Acquisition
Image Formatter
Defect Correction
- On-Board memory block
- Up to 2GB of on-board memory to store images
- Transfer from host or Acquisition supported
(allow to test processing section from host
images) - Large bandwidth to memory allow multiple transfer
to occurs simultaneously 5.3 GB/sec - Transfers from/to memory are handle by highly
optimized DMA engine
On-board Memory
Image Processing
9Anaconda Vision Processor
Acquisition
Image Formatter
Defect Correction
- Image Processing Block
- Modular and Scalable architecture
- FPGA section for mathematic acceleration
- CISC processor for complex algorithm not suitable
for FPGA implementation - User can use existing design or design his own
solution - Custom processing module possible
On-board Memory
Image Processing
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- Typical Application 1 Medical imaging
- Characteristics
- 1024 x 1024, 12-bits, 30 fps
- Noisy image
- Cost-sensitive
- Required processing
- Image correction
- Image Enhancement
- Display control
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- Typical Application 1 Medical imaging(Contd)
- Image Correction
- Flat-field correction to guarantee field of view
uniformity - UnWarp compensate for camera mis-alignment and
lens induced deformation - Note UnWarp consist in a function that perform
pixel relocation.
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- Warp used to correct perspective
- Original image Corrected image
13Anaconda Vision Processor
- Typical Application 1 Medical imaging(Contd)
- Image enhancement
- Frame averaging is a good way to eliminate
gaussian noise - When object move,blurring occurs. Motion
detection is used to eliminate blurring - Convolution 5x5 with programmable kernel for
edge-enhancement
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- Typical Application 1 Medical imaging(Contd)
- Display function Make doctor analysis easier.
- Rotation Any angle with 1/64 of a degree
accuracy - Horizontal Flip allow the doctor to align
symmetrical images(left and right) - Image Inversion (Negative)
- Anaconda can perform all theses steps in
real-time with no Host CPU usage
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- Typical Application 1 Medical imaging(Contd)
- Anaconda Demonstration
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- Typical Application 2 Wafer Inspection
- Characteristics
- High-speed linescan camera
- Processing use Golden image subtraction
- Large reference images
- Amount of data to process 150-300 MB/sec
- Required processing
- Alignment
- interpolation (Affine transform)
- Subtraction, Threshold, RLE
- Large on-board memory
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- Typical Application 2 Wafer Inspection(contd)
- Alignment process Execute Area-based search on
CISC - Minimize image transfer between host and Anaconda
- CISC has direct access to on-board memory
- Search results (Scaling, Rotation and
Translation) are sent to processing FPGA
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- Typical Application 2 Wafer Inspection(contd)
- Interpolation FPGA-based. Process data at 90
MB/sec - Search results are used to generate Affine
transform matrix (valid for rigid body object) - Interpolation (Affine transform) is accurate to
sub-pixel and compensate for all three parameters
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- Typical Application 2 Wafer Inspection(contd)
- Subtraction/Threshold/RLE FPGA perform at no
cost. - Operation is pipeline with interpolation step
- Results are available to CISC or sent down to the
Host - Data reduction make transfer time negligible
- Blob analysis is done on the host or CISC
- Solution 2-3 Anacondas can process in real-time
the latest linescan camera (320MB/sec)
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- Typical Application 3 Flat-Panel inspection
- Characteristics
- High-speed area scan camera
- Multiple processing branch in parallel
- Simple calculation but numerous
- Amount of data to process 300 MB/sec
- Required processing
- Operation performed simultaneously
- Multiple multiplications per pixel
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- Typical Application 3 Flat-Panel inspection
- Solution
- FPGA processing has enough memory bandwidth
- Multiple multiplication performed in parallel
(132 multiplication at 133 MHz) - 17 556 Millions Multiplication per sec
Equivalent to 10 PCs running at 1.8 GHz
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- Typical Application 4 Object Profiling
- Characteristics
- High-speed area scan camera
- Extremely high frame rate 10 000 fPS
- Need to horizontal find peak
- Amount of data to process 600 MB/sec
- Basler A504
- Required processing
- Detect maximums for each horizontal pixel
- Output only peak location with sub-pixel accuracy
- Typical applications PCB, FPD
23Anaconda Vision Processor
- Typical Application 4 Object Profiling (contd)
- Solution
- On-board processing using FPGA
- Data reduction 30 times less data to host
- Host processing becomes easy
- High accuracy results with minimum Host CPU load
- Host CPU can handle multiple cameras
simultaneously
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- Other possible applications
- Print inspection
- AOI inspection
- Color image processing
- Document archiving with JPEG compression
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- Algorithm Development on Anaconda
- Two options
- Done by Coreco Project description in SOW
- Customer develop himself Need Anaconda
Development kit
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IMAGE PROCESSING UNIT
DDR (512 MB)
2 GB/s
FPGA XC2VP20 or XC2VP30
Data to/From Main Board
1 GB/s
1.5 GB/s
SBSRAM (16 MB)
FPGA Register I/F
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- Algorithm Development on Anaconda
- FPGA design can be done using
- Celoxica Handle-C High-level C like language for
FPGA design - VHDL using standard Xilinx development SW
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- Algorithm Development on Anaconda
- FPGA section
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- Coreco provide Celoxica or VHDL components to
interface with the outside - Image bus High-speed bus dedicated to image
transfer - FPGA internal registers
- Dedicated DDR memory banks
- High-speed SBSRAM memory banks
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- Algorithm Development on Anaconda
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- Complete Design Flow
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- Algorithm Development on Anaconda
- Host application
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- The host program needs to
- Configure the acquisition
- Load the FPGA binary file
- Configure Data transfers from/to the FPGA
- Write to FPGA internal registers
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- Algorithm Development on Anaconda
- Host application use SaperaLT Classes
- New classes created for Anaconda
- Anaconda demo programs are using them
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- Our Goal is???
Make host application development EASY
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- Algorithm Development on Anaconda
- PowerPC development
- Need to use CodeWarrior cross-compiler from
Metrowerks - SW Project already exists to speed-up development
process - Anaconda PowerPC API make communication easy
-
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- Algorithm Development on Anaconda
- Included in the PowerPC API
- Messaging between Host and PowerPC
- Altivec optimized Sapera processing library
- Advanced functions like search
- Note PowerPC has direct access to on-board DDR
- SW development is easy, no extra data transfer
-
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- Anaconda Development Tools
- Part number exist for complete development system
- Include
- Anaconda
- PowerPC cross-compiler
- FPGA tools (Celoxica or Xilinx)
- Required Sapera Software
- Optional Tools FPGAChipscope or PowerPC
PowerTap emulator -
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- Anaconda Development Tools
- Build-in Diagnostics
- Image Bus monitoring tool
- Detailed timing module Log transfers completion
and other events -
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37Anaconda Vision Processor
- Anaconda Competition
- Matrox Odyssee Family
- Not scalable
- ASIC lack flexibility
- SBS Tsunami
- Not a dedicated imaging company
- Difficult to use
- No CISC possible
38Anaconda Vision Processor
39Anaconda Vision Processor
- Flexibility
- Processing Power
- Competitive Price
- Three good reasons to design with the Anaconda
- Thanks
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