Computer Systems

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Computer Systems

• Peripheral Programming (I/O)

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Peripheral Programming

• Peripheral programming is one of the most
  important reasons for studying assembly language.
• Implementing device drivers as interface between
  programs and I/O devices
• Three strategies
• (programmed) polled I/O
• interrupt-driven I/O
• direct memory access (DMA)

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Programmed I/O

• No special instructions for I/O
• Memory-mapped I/O
• I/O port is treated exactly like a memory
  location.
• Some I/O ports have more than one internal
  locations
• treated like a block of memory locations

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Memory-mapped I/O
8003
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Programmed I/O

• The following program does not work.
• The I/O operation is much slower than CPU
  execution! ? Data will be lost
• ? Flow control needed

Transmit 256 bytes to display OutPort EQU
8001 DataBlk EQU 2000 Size EQU
256 LEA DataBlk,A0 MOVE.W
Size-1,D0 Again MOVE.B (A0),OutPort DBRA
D0,Again
DBRA Dn,Label RTL Def. Dn ? Dn-1 IF Dn
? -1 THEN PC ? Label
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Programmed I/O - Polling

• The I/O port includes 2 registers data register
  and status register.
• The data register is used to transfer the data.
• The status register tells CPU if the data
  register is ready.

Memory
8000
8002
ERR
RDY
0
7
8
15
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Programmed (Polled) I/O
OutPort EQU 8001 Status EQU
OutPort2 DataBlk EQU 2000 ERR EQU
0 RDY EQU 7 Size EQU
256 LEA DataBlk,A0 MOVE.W
Size-1,D0 Again BTST RDY,Status BEQ
Again BTST ERR,Status BNE
Error MOVE.B (A0),OutPort DBRA
D0,Again Error

• The polling loop is the waste of CPU time.

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Interrupt-driven I/O

• No polling loop.
• The I/O can request service from the CPU by
  interrupting the CPU.
• The CPU responds to the interrupt by executing
  interrupt handling routine.
• The CPU returns from interrupt handling routine
  to the former execution.

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Program Flow of Interrupt
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Interrupt-driven I/O
IRQ1
IPL0
IPL1
IPL2
IRQ7
FC0
IACK1
FC1
FC2
A1
IACK7
A2
A3
Processor
Status
I2I1I0
Memory
CPU
Address Bus
Data Bus
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Interrupt-driven I/O

• IRQ Interrupt request line, from I/O to CPU.
• IACK Interrupt acknowledge, from CPU to I/O
  when CPU is ready to serve interrupt.
• After I/O receives IACK, it provides the CPU
  with the interrupt vector number (IVR) to tell
  CPU where the interrupt handling routine is.
• The CPU pushes the current PC and the status
  registers onto the stack.
• The CPU branches to the interrupt handling
  routine by loading PC with the interrupt vector.

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Difference between a subroutine and an interrupt
request

• Invocation
• Subroutine The programmer explicitly uses BSR
  to branch to a subroutine
• Interrupt request An external device, such as
  I/O, uses hardware signal to interrupt the CPU,
  and then uses IVR to tell CPU where the interrupt
  handling routine is
• Return
• Subroutine RTS to return to caller
• Interrupt RTE to return to normal execution.

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Interrupt-Driven I/O
OutPort EQU 8001 Status EQU OutPort2 IVR EQU
OutPort4 DataBlk EQU 2000 RDY EQU 7 INT EQU
1 Enable EQU 2 SetUp MOVE.B VecNum,IVR LEA
DataBlk,A0 BSET Enable,Status RTS Agai
n MOVE.B Status,D0 BTST INT,D0 BEQ
Exit BTST RDY,D0 BEQ Exit MOVE.B
(A0),OutPort Exit RTE
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Direct Memory Access

• How does the CPU transfer a block of data to a
  peripheral?
• Point to source of data
• REPEAT
• Read a byte of data
• Transfer it to the peripheral
• Point to next data location
• UNTIL All data has been transferred
• Is memory-mapped I/O or interrupt-driven I/O
  good for this task?

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Direct Memory Access

• Interrupt-driven I/O is slow, since a von
  Neumann machine usually requires two accesses
  per instruction.
• One access to read the instruction and one to
  access the operand (data).
• To transfer a block of data, the direct memory
  access (DMA) is faster.
• Under DMA, the I/O transfer the data directly to
  or from memory without the intervention of the
  CPU.

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Data transfer using DMA

• 1) The CPU sets up the DMA controller by telling
  DMA controller
• - the amount of data needs transfer.
• - transferred to (read) or from (write) memory
• - where the data transferred to/from in the
  memory
• 2) The CPU releases the control of the data bus
  and the address bus to the DMA controller (cycle
  stealing).
• 3) The DMA controller starts transfer of one data
  unit when the data unit is ready.
• 4) After the DMA controller completes the
  transfer, it releases the control of data and
  address buses to the CPU.
• 5) If there are more data, go to step 2)
• 6) The DMA interrupts CPU to signal the
  completion of data

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How Does DMA Affect Performance?
Memory
CPU
Bus
DMA Controller
I/O Controller
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