FE8113

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FE8113 High Speed Data Converters
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Part 2 Digital background calibration
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Gain errors and calibration- Introduction to
gain error calibration and test signal injection
in pipelined ADCs
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Pipelined ADC
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Digital error correction
1 bit, no error correction
1.5 bits, error correction
Offset translates directly to distortion at the
output
Offset within /-Vref/4 corrected by redundant
bits
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MDAC gain error
f1
f2
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MDAC gain error
f2
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Pipeline with gain error
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Pipeline with gain error
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Calibration of gain error
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Calibration of multiple stages
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Calibration, alternative implementation
(Digital scaling factors between the stages are
not shown here)
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Test signal injection
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Stage transfer function (TF)
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Stage TF with Vref/4 test signal
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Stage TF, modified test signal, tsmod
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MDAC, holding phase, test signal injection
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Test signal at ADC output
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Measuring error energy
Correlate over a blocklength (BL) of millions of
samples
Error energy at the output, use this to adjust
digital coefficient
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List of Papers

• Test signal injection
• E.Siragusa, I.Galton A Digitally Enhanced 1.8-V
  15-bit 40-MSample/s CMOS Pipelined ADC
• Skip ( fill)
• U-K.Moon, B-S.Song Background Digital
  Calibration Techniques for Pipelined ADCs
• E.B.Blecker et.al Digital Background
  Calibration of an Algorithmic Analog-to-Digital
  Converter Using a Simplified Queue
• Slow-but accurate parallel ADC
• S.R.Sonkusale et.al Background Digital Error
  Correction Technique for Pipelined Analog-Digital
  Converters
• X.Wang et.al A 12-bit 20-Msample/s Pipelined
  Analog-to-Digital Converter With Nested Digital
  Background Calibration
• J.P.Keane et.al Digital Background Calibration
  for Memory Effects in Pipelined Analog-to-Digital
  Converters
• Reference voltage scaling
• J.Ming, S.Lewis An 8-bit 80-Msample/s Pipelined
  Analog-to-Digital Converter With Background
  Calibration
• S.Sonkusale, J.Van der Spiegel Mixed-Signal
  Calibration of Pipelined Analog-Digital
  Converters
• Comparator Dithering
• A.Gines et.al Full Calibration Digital
  Techniques for Pipeline ADCs
• J.Keane et.al Background Interstage Gain
  Calibration Technique for Pipelined ADCs
• J.Li et.al Background Calibration Techniques
  for Multistage Pipelined ADCs With Digital
  Redundancy
• Others
• A.Abdelatty, K.Nagaraj Background Calibration
  of Operational Amplifier Gain Error in Pipelined
  A/D Converters
• K.El-Sanakry, M.Sawan A New Digital Background
  Calibration Technique for Pipelined ADC