Status HV

1
Status HV

• visited Athens group Jan, 29 - 31
• prototype development progressing
• still parallel voltage regulation scheme
• encountered problems with ADC for current
  monitoring
• need input
• speed of protection circuit to be defined is
  20 ms acceptable?
• on fault condition is 2 kV-gt 1 kV and then reed
  relais or no reed relais at all possible
• level of zero current measurement

2

• What we have done
• We have designed and constructed PCB cards, with
  all the
• components on it, for 6 different current
  monitoring topologies.
  
• 
  (4 layers)
• Also auxiliary power supply board was designed
• and build in order to provide power to both
• To the high voltage stand components and to the
  low one.
• 
  (2 layers)
• AIM
• 1.To choose the most appropriate topology.
• 2.To validate the choice of the components.
• 3. To measure the power consumption of the system
  in order to improve the designed auxiliary power
  supply.
• 4. To develop the first level communication
  software
• between the local mController and the
  active components.

3

• MAIN
  COMPONETS
• Master Voltage where a nominal ceiling voltage is
  provided to the Slave system
• Reed Relay to switch on-off the power to the 6!
  number of channels
• Reed Relay to switch on-off the power to a single
  chamber
• LOW VOLTAGE SITE COMPONENTS
• Shunt Regulator (H.V transistor
• Adder amplifier, Error amplifier, switching off
  transistor?)
• High Accuracy Voltage Divider(500MOhm
• 24 bit 6 S?ADC for measuring the output voltage
• 12 bit 6 DAC system for biasing the two
  transistors in (3)
• Microcontroller
• Auxiliary power supply
• HIGH VOLTAGE SITE COMPONENTS
• Current Sensing Resistor
• High precision Ultra Low noise and input current
  amplifiers
• Single 24 bit S?ADC3in3out Optoisolators per
  channel 6
• Auxiliary power supply per channel

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5
Reed relays

• The 5 KV (3KV switching) reed relay functions
  normally up to 50 Gauss.
• The 3KV (1KV switching) up to 20 Gauss.
• Hence both relays need a Faraday cage.
• This can be done either at the level of card
• or at the level of crate or rack.

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To DO (lead free!!)

• New design, construction and test of the
  auxiliary power supplies.
• New design,construction and debbuging one/two
  boards with 6 channels.
• Design , construction and debbuging the total
  digital system.
• (canbus microcontrollers)
• HOW many Canbuses/rack!!
• System Integration
• Mechanical design (accuray of card size and
  backplane external connector, possible field
  isolation, connectors, spacers etc. )
• Order of components.

8
The Control System of the TRD-HVDSProgress
ReportAthens University

• TRD-HV meeting
  Athens,30/1/2004

9
TRD
FSM?
Marc R. Stockmeier, 25/05/04
Database(s)
PVSS II
PVSS II
PVSS II
Control room (ACR)
OPCclient
DIMclient
User interface
Ethernet
GWG
ST/CV
PVSS II
PVSS II
PVSS II
PVSS II
OPC client
OPC client
PVSS II
ISEG OPCserver
Wiener OPCserver
SchneiderOPCserver (?)
DIMclient
Modbus/TCP
DIMclient
PCI-CAN
PCI-CAN
C
C
E
E
E
E
C
ISEG
PLC
DIMserver
EthernetSwitch
PLC
DCS board
E
ELMB
C
Gas
Wiener
CoolingPlant
Controlled Distribution Box
E
HV-drift
LV
Data optical
DIMserver
Detector
Detector
DCS board
Detector
Detector
High Voltage
Low Voltage
FEE
Gas system
Detector Cooling
10
PVSS instructions

• HVDS (card) status set,
  read
• card temperature read,
  alarm
• card input voltage read
  
• channel status
  set, read
• desired voltage/current set,
  read
• actual voltage/current read
• max allowed voltage/current set, read
• max voltage/current is exceeded read, alarm
• start ramping up/down set
• stop ramping
  set

11

• ramp speed up/down set, read
• max allowed ramp speed set, read
• period of transmitted V, I
• on normal operation set, read
• period of transmitted V, I
• while ramping set,
  read
• order all actual data for one
• channel (status messages) set

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Future work

• Define conditions for error messages and
• alarms.
• Implement the FSM to continue the development of
  the HVDS control according to the standard HV
  state diagram in the ALICE DCS.