Semiconductor Memory Design

1
Semiconductor Memory Design

• Introduction
• MOS Decoder
• Static Random-Access Memories (SRAMs)
• Content-Addressable Memories (CAMs)
• Field-Programmable Gate Arrays (FPGAs)
• Dynamic Random-Access Memories (DRAMs)
• Read-Only Memories (ROMs)
• EPROM EEPROM
• Flash Memories
• FRAM

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Memory Organization
May select 1, 4, 8, 16,32, 64 Col. In a Row
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Memory Design
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Memory Timing
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Memory Decoders
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Two-Level Decoder (6-bit addr)
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Ex 8.1 Sizing of Two-Level Decoder

• Size the decoder by using FO4 rules (optimal
  stage4) and Cin(LE ?BE? Cout)/4 for each stage
• Output loading1
• Branch Effort (BE) of pre-decoder16

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Ex 8.1 Solution

• LE NAND3 5/3
• Input C (5/3)(1/4)2
• BE(preDec) 16
• Cin,inv 16 (5/3)(1/4)3
• Cin,nand2 16(4/3) (5/3)(1/4)4

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SRAM Cell

• Operations

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SRAM Cell Layout
M2

• ?30??40?

CWL/cell(2CgateCwire)
Cbit(CS/DCwireCcontact)
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Wordline and bitline
Cword(2CgateCwire)? /row
Cbit(CS/DCwireCcontact)? /col.
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Read operation

• IM3 Sat IM1 lin
• Icell C bit ??V/??
• See Ex. 8.2 in pp. 373-374

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Write operation

• IM6 Sat IM4 lin

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SRAM Column I/O Circuitry

• Column Pull-ups

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PC Circuitry
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Column Selection (1)
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Column Selection (2)
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Write Circuitry
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Read Circuitry
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Sense Amplifier(1)
Differential SA
?? Cout ??V/ Iss
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Sense Amplifier(2)
Latch-based
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Replica for SA and CLK enable

• SenseEnable Same delay of Bitline

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Replica Cell design

• To match the timing of actual column delay
• 0.18V in 256 celsl
• 1.8V in 26 cells

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Memory Architecture
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Divided WL to Reduce PD Delay
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Bitline Partitioning to Reduce Delay
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Content-Addressable Memory

• Called Associative Memory
• Lookup Scheme
• Tag Previous stored keyword
• Store randomly
• SRAM architecture
• Used in Cache
• As Internet routing
• Table

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CAM Lookup Array

• ? Diff XOR1
• NMOS on
• Machi 0
• ? Same XOR0
• NMOS off
• Machii1 (precharged)
• Select only one or none row

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CAM Cell

• M7, M8, M9, M10
• XOR
• Compare (q, q) with (Tagline, Tagline)
• 20 to 30 gt Area of SRAM cell
• Taglines
• must start low to
• avoid discharge in precharge phase

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SRAM Array in CAM

• Invalid rows if not fully used
• Timing is critical since Matchlines are initially
  all prechaged
• Write data same as SRAM operations except
  Tagelines start low

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Modified CAM Cell

• Improve Speed
• M7 or M9 on if Gate1
• GND passes and waits for Tagline signals
• In Original Cell
• Tagline signals arrive
• Then GND can passes

Original Cell
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Field-Programmable Gate Array

• Rapid Implementation
• Verify function but not timing
• Overall architecture
• Routing Channel
• I/O blocks
• PLBs

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FPGA Architecture
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PLB Structure
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PLB Structure Example
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Programmable Connections
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I/O Block
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Dynamic RAM Evolutions

• SRAM w/o pull-up
• 3T DRAM

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DRAM ell
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DRAM Configuration

• Dummy cells with half Cap.

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Sense-refresh Circuitry
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Block diagram of 64kbit DRAM
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Read-Only Memories
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ROM Arrays
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Current SA
Current Mirror
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EPROM
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EPROM Write/Erase Processes
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EEPROM
FN tunneling
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EEPROM write/Erase
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EEPROM Read
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Flash Memory

• NOR Structure
• Write Hot Carriers Injection
• Erase Fowler-Nordheim Tunneling

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Write and Erase
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Flash Read Operation
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NAND Flash
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FRAM

• Ferroelectric material
• Nonvolatile
• Destructive read-out
• Need write back similar to DRAM
• Drawback (not semiconductor memory)
• Cost, Speed, Size
• Advantages
• Less power
• high density/reliability

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FRAM

• Cap Perovskite Crystal be polarized in 2
  directions
• Loigc-1 Vcc
• Logic-0 ?Vcc

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Summary of Semiconductor Memories
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Comparison Table
Endurance Cycle 102 105 106 1010-1012
Cell Size S L S S
Speed F Med F F
Power H Med L L
Erase typ UV FN FN Polarize
Erase Res. Full Mem Bit/Byte Block Bit
Memory EPROM EEPROM Flash FRAM
Prog type HCI FN HCI/FN Polarize