CHAPTER TEN | INPUT/OUTPUT

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CHAPTER TEN INPUT/OUTPUT
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INTRODUCTION
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DATA TRANSFERS
usually occur when peripherals are located within
the same computer as the CPU because their close
proximity allows them to share a common clock and
because data doesnt have to travel very far
physically, which becomes a concern at higher
clock frequencies.
uses control signals and their associated
hardware to coordinate the movement of data.
These data transfers do not require that the
source and destination use the same system clock.
There are four types of asynchronous data
transfers, distinguished by whether the source or
destination initiates the transfer, and by
whether or not handshaking is used.
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Source inputs its data, then strobes a control
signal for a set amount of time. Destination
device reads in the data during this time.
Source then deasserts the strobe and stops
outputting data.
Destination device transmits a data strobe
signal to the source device, which after a brief
delay, makes data available. After a set delay
to ensure that valid data is ready, the
destination device reads in this data and
deasserts the data strobe, causing the source to
stop transmitting the data
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HANDSHAKING
The aforementioned data transfers are appropriate
for devices that occur within a set amount of
time, but arent necessarily applicable to
devices that dont require the same amount of
time for every transfer. These devices use
handshaking to coordinate their transfers.
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Source sets data request signal high and then
makes valid data available to destination device.
After a delay to allow the data to stabilize, the
destination device reads in the data. Once the
destination device has read the data, it sends a
data-acknowledge signal to the source.
Analogous to source-initiated data transfer
except that the data acknowledge signal is
replace with a data-ready signal.
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INTERRUPTS
A mechanism for alleviating the delay caused by
the uncertainty of when devices will be ready and
for maximizing system performance External
Interrupts Internal Interrupts Software
Interrupts
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external
External interrupts are used by the CPU to
interact with I/O devices. External interrupts
improve system performance by allowing the CPU to
execute instructions, instead of just waiting for
the I/O device, while still performing the
required data transfers. External interrupts can
also be used to initiate transfers, rather than
to signal event completion.
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internal
Internal interrupts occur entirely within the
CPU no I/O devices play any role in these
interrupts. Some interrupts in this class are
purposely introduced as part of the systems
function. Internal interrupts can also be used to
handle exceptions that occur during the execution
of valid instructions.
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software
Software interrupts are generated by specific
interrupt instructions in the CPUs instruction
set. They act like subroutine call statements
except they always go to a specific address so
they do not explicitly specify the address of the
handler routines.
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PROCESSING
An interrupt triggers a sequence of events to
occur within the computer system. These events
acknowledge the interrupt and perform the actions
necessary to service the interrupt. These events
only occur if the interrupt is enabled. The
software service to the interrupt is called the
handler, essentially a subroutine. Regardless of
the configuration of the handler routine(s), each
interrupt is followed by the following sequence
of events Do Nothing(until the current
instruction has been executed) Get the Address
of the Handler(vectored interrupts only) Invoke
the Handler Routine
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DIRECT MEMORY ACCESS
Allows us to bypass the CPU and transfer data
directly from the I/O device to memory.
A DMA controller implements direct memory access
in a computer system. It connects directly to the
I/O device at one end and to the system buses at
the other end. It also interacts with the CPU,
both via the system buses and two new direct
connections. To transfer data between an I/O
device and memory, the DMA controller requests
control of the system buses, and once in control,
performs the desired data transfers. Once done,
the DMA controller no longer needs to use the
system buses so it gives control back to the CPU.
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illustration
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burst mode
In Burst Mode, an entire block of data is
transferred in one contiguous sequence. Once the
DMA controller is granted access to the system
buses by the CPU, it transfers all bytes of data
in the data block before relinquishing control of
the system buses back to the CPU. This mode is
useful for loading programs or data files into
memory, but renders the CPU inactive for
relatively long periods of time.
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cycle-stealing mode
Cycle Stealing is used for system in which the
CPU should not be disabled for the length of time
needed for burst transfer modes. In cycle
stealing, the DMA controller obtains access to
the system buses as in burst mode, however, it
transfers one byte of data and then returns the
control of the system buses to the CPU. It
continually issues requests, transferring one
byte of data per request, until it has
transferred its entire block of data. The data
block is not transferred as quickly as in burst
mode, but the CPU is not idled for as long as in
that mode.
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transparent
Transparent mode requires the most time to
transfer a block of data, yet it is also the most
efficient in terms of overall system performance.
In transparent mode, the DMA controller only
transfers data when the CPU is performing
operations that do not use the system buses. The
primary advantage of transparent mode is that the
CPU never stops executing its programs. The DMA
transfer is free in terms of time. However,
the hardware needed to determine when the CPU is
not using the system buses can be quite complex
and relatively expensive. In addition, more
advanced CPUs overlap their internal operations
and use the system bus almost every cycle. For
these reasons, this mode is generally not used in
spite of its performance advantages.
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I/O PROCESSORS
DMA controllers are only capable of transferring
data, and in some cases, data needs to be
manipulated once it is read from the I/O device,
which introduces the need for I/O processors,
which essentially perform the same functions of
DMA controllers in addition to much more.(In
fact, they usually incorporate several DMA
controllers within their circuitry.) Generally
speaking, I/O processors handle all of the
interactions between the I/O devices and the CPU.
The CPUs only direct I/O interaction is with the
I/O processor itself.
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illustration
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SERIAL COMMUNICATION
Used to interact with devices outside the
computer. The connected devices do not share a
common clock and must synchronize their data
transfers. They transfer individual bytes of
data, rather than large blocks.
more efficient it transmits blocks of data in
frames, which consist of leading transmission
data, the data, and trailing transmission
information. Despite the word synchronous in the
name, the two systems communicating generally do
not share a clock. Instead, information is
included as part of the transmission that allows
devices to synchronize their clocks.
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CONCLUSION