TDC in ACTEL FPGA

1
TDC in ACTEL FPGA

• Tom Sluijk
• Hans Verkooijen
• Albert Zwart
• Fabian Jansen

2
Upgrade LHCb

• After upgrade of LHCb there is no L0-Trigger.
• Need a TDC that can make a time stamp every Bx.
• Radiation environment.
• At least 32 channels.
• About 4 bit TDC resolution to minimize the output
  data rate.

3
TDC in Actel FPGA

• Design of TDC in ACTEL Proasic3E FPGA because of
  the radiation properties
• Design based on the Muonlab TDC 2 channel TDC
  in Xilinx FPGA resolution of 500 ps, see
  http//www.nikhef.nl/hansvk/muonlab/.
• The properties of the PLL in the ACTEL Proasic3E
  FPGA do not have the fancy phase shift
  possibilities compared to the Xilinx PLL, so the
  resolution will be lower.
• First approach3 PLLs used to generate phase
  shifted 320 MHz signals of 0º, 45º, 90º and 135º
  ? bins of 780 ps. 8 ch TDC was simulated, this
  design was hard to fit. The Actel Starter Kit
  has only 2 PLLs, so this design can not be used
  for tests.
• Second approach1 PLL at 320 MHz used to
  generate 8 phase shifted 40 MHz signals ? bins
  of 1570 ps A four channel TDC is designed.

4
TDC (second approach)
BxClock
PLL 320MHz
5
Timing Diagram

6
Chip layout

• This part is used
• for 4 channels

7
Test Procedures

• The design is fitted in an A3PE1500 208 PQFP and
  programmed in the Actel Starter Kit.
• The first test to determine the DNL
• The onboard 40 MHz xtal oscillator is used as
  Bx Clock.
• An asynchronous pulse generator of 10 MHz
  generates a Hit signal with a flat distribution.
• Second test is a delay scan to determine the
  linearity
• Pulse generator of 40 MHz supplies the Bx Clock.
• This signal is also delayed with a switchable NIM
  delay with steps of 0.5 ns to get the Hit signal.

8
Test Setup
9
Hit Distribution
10
TDC Spectrum
11
Linearity

12
Scatter Plot ch1 vs ch2
13
Conclusions

• A TDC with reasonable performance can be build in
  an Actel FPGA.
• Increase of number of channels up to 32 channels
  could be possible. (see chip layout)
• The resolution is limited by the maximum PLL
  clock (350 MHz) The increase of the resolution
  by one bit might be achieved when a second PLL
  clock of 320 MHz with a phase shift of 90 is
  used.
• Temperature tests should be performed to check
  the stability of the design.