Statistical Logic Cell Delay Analysis Using a Currentbased Model

1
Statistical Logic Cell Delay Analysis Using a
Current-based Model

• Hanif Fatemi, Shahin Nazarian, Massoud Pedram
• July 25, 2006
• Department of Electrical Engineering-Systems
• University of Southern California

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Outline

• Motivation and Background
• Current Source Modeling (CSM) for the purpose of
  Logic Cell Delay Analysis under Noisy Input
  Waveforms
• Statistical Logic Cell Delay Analysis Using a
  Current-based model (Statistical CSM)
• Experimental Results
• Conclusions

3
Motivation
Key Issues in Timing Analysis

• Actual shape of the input waveform
• The down scaling of layout geometries
• Aggravation of noise effects, such as capacitive
  crosstalk
• Process variation
• The down scaling of technology
• Significant increase in manufacturing-induced
  circuit parameter variability
• Significant increase in uncertainty and
  unpredictability

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Logic Cell Timing Analysis

• Conventional logic cell delay techniques ignore
  the actual shape of the waveform
• Approximation of the input with a saturated ramp
• Given A (noisy) input voltage waveform
• Objective Determine the output voltage waveform
• Min error w.r.t. the actual shape of the output
  waveform
• Current Source Modeling (CSM) of Logic Cell
• Construct the output based on the input voltage
  and the logic cell model

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Existing CSM approaches

• KTV (Keller-Tseng-Verghese)
• A pre-characterized current source to model
  thenon-linear behavior
• Constant Miller and output capacitance to model
  theparasitic effects
• Blade
• A simpler model with no Miller capacitance
• Parasitics effects can vary significantly
  depending on input/output voltage values
• Process variation is not addressed

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Voltage Calculation using CSM

• Model the non-linear and the parasitic effect of
  the logic cell
• Series of Spice simulation to pre-characterize
  the components of CSM model
• 2-D lookup table to store the elements of the
  CSM
• Vo(tk1) Calculated based on Vo(tk) and Vi(tk),
  Vi(tk1) and the current source and parasitic
  capacitance values

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Process Variation in USDM Designs

• Circuit variability is increasing in UDSM
• Corner-based timing analysis techniques
• computationally expensive as the number of
  sources of variations increases
• Results in conservative (suboptimal) designs
• Solution Statistical Static Timing Analysis
  (SSTA)
• Objective Calculate the distribution of the
  delay
• In SSTA, any quantity of interest (slew, delay,
  slack, arrival time) is modeled as follows
• DXi ith source of variation with N(0,1)
• Sources of variation are assumed to be independent

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Statistical CSM

• Existing SSTA methods
• Approximate voltage waveform with a saturated
  ramp signal
• Modeled by the pdf of its signal arrival and
  transition times
• Ignoring the shape of the waveform in SSTA
• Gives rise to the same level of inaccuracy as in
  STA
• Solution Utilize CSM model for SSTA
• The logic elements of CSM as a function of
  process variation

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Output Voltage and Delay Distribution

• Apply the first order form associated with each
  cell element to the voltage equation
• Convert to the first order based on standard
  techniques
• The distribution of Vo at each time instance
• Calculated based on the distribution of Vo at the
  previous time instance
• Vo(t) is a Markovian process
• Compute delay distribution based on the
  calculated voltage distribution
• Ta The first time instance Vo(t) crosses the a
  value
• Idea

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Statistical CSM Delay Distribution

• P(Vo(ti)lta,Vo(ti-1)lta) can be calculated by the
  bivariate normal distribution
• Covariance of Vo(ti) and Vo(ti-1) can be
  calculated as

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Experimental Results

• HSPICE and our CSM-based results for some
  crosstalk-induced noisy waveforms
• Logic cell Minimum sized inverter in 130nm
  library

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Experimental Results

• Compared to KTV, the accuracy of delay
  calculation for the minimum sized inverter is
  improved by 8.8 (17.3) in average (max.)

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Experimental Results

• Compared to KTV, the accuracy of delay
  calculation for the AOI22 with size 10x is
  improved by 52.1 (93.4) in average (max.)

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Experimental Results

• Hspice based Monte-Carlo simulations to
  calculatethe 50 cell delay distribution
• Minimum size inverter as well as the AOI22 cell
• 3s variation of 15 for the sources of variation
• Compared the mean and the variance of the 50
  delay computed by our proposed mathematical
  approach and that of Monte-Carlo simulation

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Conclusions

• A new current-based cell delay model was
  developed to accurately capture
• various cell parasitic effects
• Cell nonlinear behavior
• Capable of constructing the output waveform
• In 130nm library
• Erroravg lt 0.7
• Errormax lt 2.4
• Large improvement for complex cells
• A new framework for Statistical-CSM presented
• Modeled the voltage waveform by a Markovian
  process
• Calculated the distribution of the delay

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• Thank you!

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First Order Model for Logic Cell Parameters

• The sensitivity coefficients derived from a
  series of SPICE simulations
• Minimum mean squared error fit is used
• Stored in a 2D look-up tables