Task IV' Integrated InputOutput Interconnections

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Task IV. Integrated Input/Output Interconnections
Paul A. Kohla, Kevin P. Martina, (Task Leaders)
Mark G. Allena, James Castracanec, Thomas K.
Gaylorda, Dennis Hessa, David Keezera, Joy
Laskara, Gary S. Maya, James D. Meindla, Serge
Oktyabrskyc Eugene Rymaszewskib, Suresh
Sitaramana and C. P. Wonga
a Georgia Institute of Technology Atlanta, GA b
Rensselaer Polytechnic Institute Troy, NY c
University at Albany Albany, NY
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Integrated Input/Output Interconnect Our
Ability to Form an Interconnection System
The 50 35 nm technology node requirements will
approach or exceed 1010 devices/chip, 10 GHz
local clock, 170 W, 300 A

• Spatial Demands Large Number of I/Os and Large
  Chip Areas
• Extremely high density of interconnections (lt 30
  ?m pitch)
• Precision and cost advantages of wafer level
  processing
• Speed and Timing Demands Very High Signal and
  Clock Speeds
• Precision and accuracy of structural units
  (electrical performance)
• 5 - 40 Gbit/s channels
• Global Interconnections

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Integrated Input/Output Interconnect Our
Ability to Form an Interconnection System

• Power and Heat Dissipation Traditional
  approaches will fall short
• High power and low noise environment
• Integration of I/O Technologies
• Different I/O Technologies- Optics, RF,
  Electrical
• Functions do not overlap
• Materials and Processing
• Thermal expansion mismatches have severe
  processing penalties
• Heterogeneous I/O technologies require
  heterogeneous materials
• Cost
• Testing and burn-in cost mitigated with more I/O
  and WL approach
• Chip-to-Module Assembly

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Integrated Input/Output Interconnect Research
Efforts

• Extreme High Density Compliant Interconnects (lt
  30 ?m pitch)
• RF-based Interconnect Networks
• Optical Interconnects
• Lower Temperature Materials and Processes
• Wafer-Level Fabrication of All Interconnect
  Approaches
• Wafer Level Test and Burn-In

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Research Driver Challenges

• Global Signal Communication
• Global and Semi-global Clock Distribution
• Achieving tens of Tb/s bandwidth
• 3-D chips
• Integration of processor and memory
• Integration of high-bandwidth optical
  interconnects
• High bandwidth from reconfigurable interconnects
• Power consumption (high and low)
• Integration of mixed technologies (digital, RF,
  MEMs, Optical)
• Form factors
• Advanced IC packaging
• Advanced systems modules

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Interconnects - Hierarchy Continuum
3-D
Chip-Chip Interconnects
System Level

• Interconnect Methods
• Electrical
• RF
• Optical

System Module
System Level Interconnects
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Chips
PWB Industry
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Chip-to-Module Assembly Needed for Full
Integration

• Non-Traditional Assembly Approaches
• CTE mismatch at very fine pitches is prohibitive
• Focussed (localized) heating
• Materials that do not require high temperature
  processing
• Non-thermal attachment processes- electroplated
  bonding
• RF- and Optical- Interconnects present special
  challenges
• e.g. Planarity, Registration, Contamination
• Common Medium (e.g. Substrates)
• Three-Dimensional Nature

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Basic Concepts of Integrated Input/Output
Interconnects
Monolithic Buildup of All Input/Output Interconnec
t and Packaging Elements
Back End of the Line
Wafer
Electrical, Optical or RF Contact Element
Compliant Interposer
Die
Flexible Electrical Lead
X-Y-Z Motion
Lens
Capacitive Coupler
RF T/R
Intra-Chip Interconnects
Silicon Wafer
Optical Source/Detector
Scribe Lane
Contact Pad
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Module Routed Inter- and Intra- Chip Electrical
Interconnects
Flexible Leads
Interposer
Chip
System Module
Intra-Chip Module Wiring
Inter-Chip Module Wiring

• Intra-Chip Module Wiring
• Route global interconnects through module wiring
• Thicker off-chip wiring reduces parasitics
• Presents new test and burn in opportunities and
  challenges

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System Board/ Mother Board (FR-4)
17 ppm/oC
50 ppm/oC
Fully Packaged ICs intact in wafer form
3 ppm/oC
During Temperature Cycling...
Fully Packaged ICs intact in wafer form
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Limits on Conventional Electrical Clock
Distribution
Bandwidth limitations of global electrical
interconnects Cu/SiO2 3

• For f3dBgt10GHz ? Lint lt .36cm
• Local driver sizing limited by
  electromigration
• Increase point-point repeaters ?
• Skew
• Jitter
• Power dissipation
• Sizing restrictions on global interconnect
• Large cycle-cycle variations in ?Idd

3 Payman Z. Ha, GSI Group
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Periphery vs. High Density Area Array Power
Distribution
Achip Apower/gnd Aclock Asignal
Periphery
Area
Power distribution area versus chip power
(Hmetal thickness, ?IR drop, npgpower supply
pads, nwiring levels) Payman Zarkesh-Ha and
James D. Meindl
n number power pins
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Design, Modeling, and Characterization of
Electrical I/O Interconnects
Modeling Arrays of Leads Center Lead and
Neighbors

• Prior Results on Simplified Compliant Lead
• 100 ?m lead LC delay lt 1 fs
• Future
• More complex higher density compliant lead with
  air gaps.
• Full RLC treatment of arrays
• Application (power, signal, clock) driven lead
  variations (impedance, density, geometry)
• Effects of signal crosstalk and -Ldi/dt power
• High frequency (f gt 10 GHz) impedance matching

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• Failure during reliability test was
• recorded when the resistance of the
• compliant leads was greater than
• 20 of its pre-reliability test value

• 50 ?m of lateral (xy) extension and
• compression recorded without
• change in initial resistance of the
• leads

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Very High Density Flexible I/O 12,000 leads/cm2

• Same fabrication process (and manufacturing
  cost) as for 1000 leads/cm2 I/O prototype

80 ?m pitch inner lead array, 160 ?m pitch outer
lead array
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Embedded Air Gaps for Highly Compliant Interposers

• Air-gap shape is dependent on the size of the
  air-gap, the overcoat material, and the
  decomposition rate and conditions

140mm air-gap overcoated with PI-2734
30mm air-gaps overcoated with UltradelTM 7501
140mm air-gap overcoated with UltradelTM 7501
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Compressible, Very High Density I/O
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Compressible, Very High Density I/O
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Air Cavities in Very High Density I/O
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Finite Element Analysis of Flexible Leads with an
Air Gap Interposer
Maximum solid interposer ?z lt 5 ?m
Air Gap
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Embedded Air Gaps

• Fabricated using UltradelTM 7501 overcoat
• Copper is electroplated slightly beyond the
  thickness of patterned PNB then etched back using
  nitric acid
• The air-gap forms leaving Cu channels overcoated
  with polymer and a thin insulating layer of
  polymer on the sides

Cu
20 mm
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Enhanced Heat Transfer via Mass Transfer Through
Porous or Air-Cavity Regions

• High performance interconnections (low
  capacitance coupling) are at the expense of
  thermal conductivity (air is poor thermal
  conductor
• Regions which have air-cavities are spatially
  close to high heat generators
• Can through - wafer, or through - interconnect
  pressure drops be developed to generate
  sufficient mass transfer for heat removal?
• Example, isothermal mass flux through smooth
  channels (100 mm long, 1-10 mm2 area, DP1 atm)
  are 10 to 100 g/cm2 s.
• Fluid mechanics modeling, advanced interconnect
  opportunities (3-D structures, air-gaps), and
  physical structures.

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Free Standing Compliant Beam Leads

• Goal produce leads completely up off the
  substrate for maximum flexibility
• Approach surface micromachining
• Technology electrodeposition through polymeric
  sacrificial layers
• High aspect ratio devices enabled
• Ultra-planarization possible

• Extend to include RF in the interconnect layer
  inductors, antennas, resonators

Surface micromachined electroplated copper
interconnect (elevation from substrate 50
microns)
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Geometric Model of Free Standing Coil Lead
Front View
Left View
Top View
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FEM Analysis (Bottom is fixed Vertical Force is
loaded on top)
Deformed Shape when Fy2.5mN
Von-mises Stress Distribution when Fy2.5mN
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Controlled Shape Formation During Plasma Etching

• The condition that gives high etch rate usually
  gives low sidewall angle and leaves rough etch
  surface.
• Sidewall angle increases with decreasing
  pressure and increasing RF power.

• An optimal condition pressure 300 mtorr
  RF power 200 W total flow rate 50
  sccm CHF3 percentage 15.
• Etch rate 1.25 ?m/min sidewall angle 70

SEM cross section of plasma etched via
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Plasma Etching Results
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Intelligent Testing of Chip-to-Module
Interconnections

• Objective Take advantage of the availability of
  wafer-scale packaging to perform fault-oriented
  wafer-scale parallel testing.
• Approach Develop smart algorithms using sensor
  fusion and possibility theory
• Collapse multiple test signals into a single
  metric for fast go/no-go testing.
• Implement fault identification/categorization
  using pattern recognition techniques.

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Wafer Level Testing
ATE
TSP- ATE Interface
TSP Support
Low energy sense
TSP - DUT Interconnects
TSP
DUT 1
DUT 2
DUT 3
Wafer
Electrical- , Optical-, or RF- Interconnects

• Develop chip-specific active electronics test
  support processor
• Test Support Processor (TSP) acts as a close-in
  semi-autonomous tester
• Multiple TSPs permit parallel testing
• ATE acts primarily an observer
• Unique challenge to develop test connections and
  procedures, especially for Optics and RF
• Develop low energy capture - non-invasive
  sensing to monitor intra-chip activity

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Optical Clock Distribution Network
Si-based Detector
Chip
Flexible Lead
Grating Coupler
Interposer
System Module
Waveguide

• H-Tree Distribution Network from Single Mode
  Waveguides
• Volume Grating Couplers
• Off-Chip Photon Sources
• Eliminates Global and Semi-Global Clock
  Electrical Power Consumption
• Integrate With RF and Electrical Interconnections

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Optical Input/Output Interconnects
Serge Oktyabrsky and James Castracane, University
at Albany -SUNY

• Objectives
• Demonstration of packaging schemes for wireless
  optical free-space I/O suitable for traditional
  planar and 3D ICs
• Implementation of a MEMS-based free-space optical
  reconfigurable interconnect system at the board
  level and demonstration of a "smart alignment"
  protocol

Target specifications for off-chipI/O optical
interconnects Single channel bandwidth gt3
Gbit/s Number of parallel channels gt1000 Power
consumption per channel lt1 mW Pitch size lt50 mm
Target specifications for VCSEL arrays VCSEL
operating current at 100 oC lt0.5 mA External
efficiency gt50
Lifetime at 100 oC gt105 hours
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Accomplishments VCSEL Arrays - Key Optical
Interconnect Component
VCSEL Emission
8x8 array of VCSELs
VCSEL cross-section
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Accomplishments Optical Switching Using
Reflective and Diffractive MOEMS Arrays
Optical switching demo with micromirror array
(DMA)
Test pattern segment generated by DMA
SEM image of diffractive MOEMS array (3 mm
ruling, 100 mm pitch)
Optical switching demo with diffractive array
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Hybrid Integration of III-V VCSEL Arrays
VCSEL
Compliant interposer

• Hybrid integration of III-V device arrays on Si
  chip using an imbedded flip-chip approach allows
• Complete processing of III-V devices on GaAs
  wafer
• Single side metallization on GaAs wafer
• Transfer of massive array of III-V devices on a
  dye or wafer level.
• Etching out or epitaxial lift-off of GaAs
  substrate to separate the optical devices to
  avoid thermal stresses in hybrid structures
• Alignment tolerance
• Wafer-level testing

• Optical backplane approach based on bonding of a
  thinned GaAs optical chip to the edge surface of
  Si chip
• Most beneficial for 3D vertically integrated
  chips
• Complete processing of III-V devices on GaAs
  wafer
• No need for separation of individual
  optoelectronic devices
• Requires flexible wiring between the Si and GaAs
  chips

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Free-Space Reconfigurable Chip-to-Module
Interconnect System

• MEMS-based diffraction grating or micromirror
  arrays for 3D free space optical interconnect
  system
• Maximum density and parallelism compared to other
  interconnect media
• Reconfigurability
• Smart alignment protocol based on scanning and
  optimizing the optical channels for the highest
  response and the lowest crosstalk

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Wireless Inter/Intra Chip Connections Microtooth

• Goals
• Establish Framework for Ubiquitous Wireless
  Interfaces
• UCLA/GT Team Investigate Required
  IC/Interconnect Architectures
• Provide Roadmap through Prototype Demonstrations
• Establish Interconnect Technology
• Establish Testbed/Verification
• Impetus
• Reconfigurable Wireless Networks are Evolving
  (e.g. Bluetooth)
• Can this Impact Inter/Intra Chip Connections?
• Potential for New Chip Level Communication
  Paradigms

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Wireless Inter/Intra Chip Connections Microtooth

• Challenges
• Develop Specifications for 10 cm Communication
  Systems
• Seamlessly Complement Other RF Communication
  Systems (e.g. Bluetooth with a 10 cm range)
• Establish Design Rules for Both Required IC and
  Packaging Content
• Antenna Design Rules
• Power Requirements
• Signal Distribution
• Interconnect and Isolation Structures
• Identify and Develop Prototype Demonstration
  Vehicles

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Evolution of Research
Develop in Cad Environment
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Previous Work Real-Time RIE Control

• Real-time control system with two adaptive neural
  networks

Laser Interferometer

• A second neural network model relates sensor data
  to measurable responses

Interferometer
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Proposed Future Work Modeling and Control of
Microwave Curing
targets
frequency (fc, Df)
temperature
Neural Network Controller
Process Model
sweep rate
mWave Cure System
FTIR
ramp rate
power

emissivity
error1
-
error2

Sensor Output Model
Dielectric Constant Dielectric Loss CTE Adhesion R
esidual Stress Moisture Uptake Tg
-

• Approach Variable frequency microwaves for
  polymer curing
• Goal High temperature processing without CTE
  mismatch penality (for which there is no known
  solution).

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Integrated Passive Structures E. Rymaszewski -
RPI

• To equip the interposer with high performance
  decoupled power distribution planes (high C, very
  low L)
• To use materials and fabrication processes which
  are compatible with the rest of the interposer
• To achieve capacitance densities in several
  hundred nF/cm2 range, inductances in pH range,
  breakdown voltages above 10-25 V, and leakage
  current densities below 1 ?A/cm2
• Design and fabricate interposer samples in which
  a thin ceramic film is placed between the ground
  and power planes
• Perform electrical evaluations of the power
  distribution properties

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Fabrication of Thin Film Ceramic Dielectrics -
TaOx

TaOx 35 O
2
305 Å
565 Å
1090 Å
2745 Å
Deposition Temp. ? 200 C

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0.05
E
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Future Directions Integration of Input/Output
Interconnections

• Design, Fabrication and Test Prototypes for
• High Density Compliant I/O connections
• I/O density matches the last level of on-chip
  metallization
• Complete electrical mechanical modeling of
  single leads and arrays
• Integration
• RF components such as capacitive couplers
• Optical clock distribution components such as
• waveguides and grating couplers
• Embedded passives and decoupling capacitors for
• effective power distribution and noise isolation
• Compliant interconnects on airgaps to enable
  wafer level testability
• Wafer level test and burn in of integrated
  electrical, optical and RF I/O

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Enhanced Heat Transfer via Mass Transfer Through
Porous or Air-Cavity Regions

• High performance interconnections (low
  capacitance coupling) are at the expense of
  thermal conductivity (air is poor thermal
  conductor
• Regions which have air-cavities are spatially
  close to high heat generators
• Can through - wafer, or through - interconnect
  pressure drops be developed to generate
  sufficient mass transfer for heat removal?
• Example, isothermal mass flux through smooth
  channels (100 mm long, 1-10 mm2 area, DP1 atm)
  are 10 to 100 g/cm2 s.
• Fluid mechanics modeling, advanced interconnect
  opportunities (3-D structures, air-gaps), and
  physical structures.