Lecture 7: Hardware/Software Systems on the XUP Board

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ECE 412 Microcomputer Laboratory

• Lecture 7 Hardware/Software Systems on the XUP
  Board

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Outline

• Overview of Linux/HW interaction on the XUP board
• Resources available for you on the board
• Discussion of the Virtex-II Pros BlockRAMs

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Review Questions

• What function does the mmap() call serve in
  implementing memory-mapped I/O?
• What are the two alternatives of communicating
  between the devices and the processor? Comparison
  of these methods?

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Review Questions

• What function does the mmap() call serve in
  implementing memory-mapped I/O?
• mmap() causes a set of device registers or other
  data to be mapped onto a region in the address
  space
• What are the two alternatives of communicating
  between the devices and the processor? Comparison
  of these methods?
• Polling
• takes CPU time even if no requests pending
• can be better if the processor has nothing better
  to do and has to respond to an event ASAP
• Interrupts
• no overhead when no requests pending
• can be better if the processor has other work to
  do and the time to respond to events isnt
  absolutely critical (need context switching)

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The XUP Board
XUP Board
FPGA
PowerPC
FLASH Card
VGA
Audio In/Out
Serial Port
Ethernet
SDRAM
I/O Connector
I/O Connector
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Pure-Hardware System
XUP Board
FPGA
PowerPC
FLASH Card
VGA
Audio In/Out
Logic
Serial Port
Ethernet
SDRAM
I/O Connector
I/O Connector
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XUP Board as PC
XUP Board
FPGA
PowerPC
FLASH Controller
FLASH Card
VGA Controller
VGA
PLB Bus
Audio Controller
Audio In/Out
UART Controller
Serial Port
Ethernet Controller
Ethernet
SDRAM Controller
SDRAM
I/O Connector
I/O Connector
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ECE 412 Approach -- HW/SW System
XUP Board
FPGA
PowerPC
FLASH Controller
FLASH Card
VGA
Logic
PLB Bus
Audio In/Out
Serial Port
UART Controller
Ethernet
SDRAM Controller
SDRAM
I/O Connector
I/O Connector
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MP2 Configuration
XUP Board
FPGA
PowerPC
FLASH Controller
FLASH Card
VGA
Logic
PLB Bus
Audio In/Out
Core
OPB
Serial Port
UART Controller
Ethernet
SDRAM Controller
SDRAM
I/O Connector
I/O Connector
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Embedded Power PC 405 Core
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PPC

• Functional blocks
• Cache units (ICU and DCU, 16 KB each)
• Memory Management unit
• Fetch Decode unit
• Execution unit
• Timers
• Debug logic unit
• It operates on instructions in a five stage
  pipeline consisting of
• fetch, decode, execute, write-back, and load
  write-back
• Most instructions execute in a single cycle,
  including loads and stores.

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Creating a HW/SW System

• Custom logic needs to conform to bus/interface
  protocols
• Well provide documentation about this
• For MP2.1, we provide a prototype for the
  function you have to write (In VHDL)
• Assemble custom logic, IP cores, software into a
  package that can be downloaded onto the board
• EDK tool creates bit file for FPGA
• SystemACE HW loads Linux/other SW off of FLASH
  card
• Can also pre-load BlockRAMs w/data as part of
  FPGA programming

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Interfaces to the PowerPC Cores

• Processor Local Bus (PLB)
• 64-bit bus that handles fast data transfers with
  the PowerPC and the peripherals
• For example, DDR controller hangs on this bus
• There is also a 32-bit bus called OPB (On-Chip
  Peripheral Bus) that handles slower peripheral
  devices
• For example, for UART and SystemACE access
• Needs to connect to PLB via a special PLB-to-OPB
  bridge
• OCM (On-Chip Memory) Controller
• Allows memory (BlockRAMs) to be accessed at rates
  comparable to the caches
• Great way to build data buffers
• Interrupt Controller
• Device Control Register
• Allows creation of a register file that is
  shared among all of the devices connected to
  the PowerPC
• Clock, Power Management
• JTAG Port

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Other Resources

• SDRAM
• Lots of space, complex interface requirements
• Controlled via IP core
• Your HW can interface with core, simplifying
  things
• BlockRAM
• Small, on-chip memory
• Can be configured in a number of ways
• Fast, simple interface

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Virtex Block SelectRAM

• 18Kb capacity and configurable at build time to
  be either
• 1 x 16K
• 2 x 8K
• 4 x 4K
• 8 x 2K
• 16 x 1K
• 32 x 512
• 136 of these on each XC2VP30 FPGA for total of
  2.4Mb total
• Dual ported, can be aggregated to form larger
  structures
• Parity bits, possible to pre-load with data in
  VHDL

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Generic Block Diagrams
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Interface Signals
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Supported Configurations

• Your VHDL will instantiate using primitives
• Each reference is an individual BRAM
• Could form larger memory block by assembling
  number of primitives, routing delay would
  determine total access time.

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Physical Location
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Read and Write Timing

• Refer to posted application notes for exact
  details
• XAPP-463 (says Spartan-3 but is applicable to our
  parts)
• XAPP-130 (basic operation, but is for early
  smaller BRAMS)

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Instantiating BlockRAMs

• Declare as components, can instantiate multiple
  copies of a component
• component RAMB16_s9
• Port ( clk in std_logic ... )
• end component
• Documentation section of the web page has
  instructions on simulating designs that use
  BlockRAM, example that links multiple BlockRAMs
  to form larger memory

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Uses for BlockRAMs

• Scratchpad memories in designs
• ROM arrays -- can pre-load BlockRAMs with fixed
  values
• CLBs are reasonably efficient at implementing
  ROMs, so dont need to use BlockRAMs unless you
  have a very big ROM
• CLBs are very inefficient at implementing RAMs,
  want to use a BlockRAM any time you need more
  than a few words of RAM/register
• Buffer for Linux/HW communication
• One simple way to move data between Linux and HW
  is to use BlockRAM buffer for data,
  interrupt/register write to signal when data is
  ready.

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Next Time

• The PLB bus