Digital Phase Follower Deserializer in LowCost FPGA

1
Digital Phase Follower --Deserializer in
Low-Cost FPGA

• Jinyuan Wu, Z. Shi

2
Motivation

• In HEP systems, sometime many channels of serial
  data must be concentrated.
• It will be nice if the data clock is not
  transmitted separately. (Just transmit a single
  data channel).
• It will be nice if it can be received in low-cost
  FPGA in which dedicated serial data receivers are
  not available.
• It will be nice if user protocol can be
  supported. (Can be 8B/10B, or can be anything
  users want).
• Examples
• TSO modules to PP modules. (500 Mbps, user
  protocol).
• FPIX2 to PDCB. (140 Mbps, user protocol).

3
Receiving Serial Data

• Data channels are de-serialized using shift
  registers.
• The clock for the receiving shift registers comes
  from
• Separate channel. (Channel-channel skew ? ).
• Same data channel.
• Clock recovery using PLL. (Phase detectionVCO).
• Dynamic phase aligner. (In Altera devices,
  choosing a correct clock phase from 8 phase
  samples).
• Digital phase follower. (For low-cost FPGA).

4
Multiple Sampling
b0
b1
b2
Quad Sampling Fs 4/UI
b0
b1
b2
b3
Triple Sampling Fs 3/UI
Double Sampling Fs lt or gt 2/UI
b0
b1
b2
b3
b4
b5

• Multiple sampling is used to determine the phase
  of the data.
• A correct sampling point is automatically chosen
  after first 0 to 1 transaction.
• The sampling point shifts following the shift of
  the data phase.
• Everything is in standard digital circuit.

5
More Notes on Multiple Sampling
b0
b1
b2
Quad Sampling Fs 4/UI
b0
b1
b2
b3
Triple Sampling Fs 3/UI
Double Sampling Fs lt or gt 2/UI
b0
b1
b2
b3
b4
b5

• In digital phase follower, since no clock
  recovery is needed, 4, 3 or 2 samples per bit
  (unit interval) are sufficient. (Not 8).
• In double sampling case, sampling rate must be
  known either less or larger than 2/UI.

6
Digital Phase Follower, Block Diagram
Q3
QF
Data Out
c0
c0
Data In
b1
Q2
QE
b0
c90
Q1
QD
Shift2
c180
Shift0
Frame Detection
Q0
c270
SEL
Multiple Sampling
Clock Domain Changing
Tri-speed Shift Register
was3
is0
was0
Trans. Detection
is3
7
Digital Phase Follower Operation
Older Samples
Selected Sample
Q3
Selected Sample
Q2
b0
Selected Sample
Q1
Selected Sample
Q0
SEL
QF
QE
QD
Newer Samples
SEL0
SEL1
SEL2
SEL3
8
Was 0, Is 3, Data Is Slower. Shift 0.
This bit has been sent to the shift register. No
duplicate recording.
Older Samples
New Selection
Q3
Q3
Q2
b1
Q2
Q1
b0
Q1
Shift2
Old Selection
Q0
Shift0
Q0
QF
SEL
QE
Tri-speed Shift Register
was3
QD
is0
was0
is3
SEL was 0
SEL is 3
Newer Samples
9
Was 3, Is 0, Data Is Faster. Shift 2.
This bit has not been sent to the shift register.
Sent it through b1, along with new selection
b0Q0.
Older Samples
Old Selection
Q3
Q3
Q2
b1
Q2
Q1
b0
Q1
Shift2
New Selection
Q0
Shift0
Q0
QF
SEL
QE
Tri-speed Shift Register
was3
QD
is0
was0
is3
SEL was 3
SEL is 0
Newer Samples
10
Simulation (1)

• This is a 4B/5B receiver working at 400Mbps,
  compiled in an Altera Cyclone device.
• The receiving clock is 0.4 slower no errors is
  seen.

11
Simulation (2)

• The same receiver running with receiving clock
  0.4 faster no errors is seen.

12
Deserializer Based on Digital Phase Follower

• Data is self-timed, no separate clock
  transmission is needed.
• The transmitter and receiver clocks can be
  independent frequency difference is
  compensated.
• User protocols are supported.
• It can be implemented in low-cost FPGA.

13
Digital Phase Follower Start-up

• Preamble 1 idle word with 0 to 1 transitions.
• In other scheme, long preambles or training
  patterns are needed.
• Frame detection defined by user. It can be
  10000000000000xxxxxxxxxx (in FPIX2).
• Data