EE 30357: Semiconductors II: Devices Lecture Note

1
EE 30357 Semiconductors II DevicesLecture Note
39 (04/29/09)Final Review

• Outline
• Semiconductor properties
• Band diagrams
• P-n junctions, Schottky junctions and ohmic
  contacts
• MOS junctions and FETs
• Bipolar transistors
• Optoelectronic devices
• Almost every slide describes a concept, or graphs
  equations associated with this concept. (C-G-E
  learning)

2

• Outline
• Semiconductor properties
• Band diagrams
• P-n junctions, Schottky junctions and ohmic
  contacts
• MOS junctions and FETs
• Bipolar transistors
• Optoelectronic devices
• Almost every slide describes a concept, or graphs
  equations associated with this concept. (C-G-E
  learning)

3
Band diagram
Case 1
Case 2
SB Figure 34 Typical band diagrams at 0 K.
SB Streetman and Banerjees Solid State
Electronic Devices
4
Fermi-Dirac Statistics and n p
EfFermi level
Streetman and Banerjee Figure 316 Schematic band
diagram, density of states, FermiDirac
distribution, and the carrier concentrations for
(a) intrinsic, (b) n-type, and (c) p-type
semiconductors at thermal equilibrium.
5
Review equations for n0 and p0

relative to intrinsic level
relative to band edges
n0 p0ni2
6
Current density J in homogeneous semiconductor
J (charge per electron)?(density of
electrons)?(average electron velocity)
(charge per hole)?(density of holes)?(average
hole velocity) qn?vn? qp?vp? qn mn
E qpmpE
?vn? mn E electron mobility electric
field ?vp? mp E hole mobility electric
field
I
Both electrons and holes contribute to total
current check units Amperes/area (typically
A/cm2)
V
7
Mobility,velocity and scattering
Velocity
Electric field
with
In Si, mean free time
8
Mobility (Temperature doping concentration
dependence)
9
High Field Effects
This is a Log-log plot Can you plot it in
linear-linear plot?
velocity saturation
Velocity overshoot in GaAs
Recall J-qnvdn (2.32)
The smaller effective mass, the larger the
mobility, generally speaking
10

• Outline
• Semiconductor properties
• Band diagrams
• P-n junctions, Schottky junctions and ohmic
  contacts
• MOS junctions and FETs
• Bipolar transistors
• Optoelectronic devices
• Almost every slide describes a concept, or graphs
  equations associated with this concept. (C-G-E
  learning)

11
Two similar semiconductors, doped differently,
before being joined in a junction. Figure 5.2
Electron affinity model
Built-in voltage (contact potential) difference
in Fermi levels of the two materials
12
Three types of heterojunctions Type I
(straddling), in which the wide-gap energy
overlaps that of the narrow gap, is the most
important Type II (staggered) and Type III
(broken gap). Figure 6.7
Type I straddling Type III broken
gap Type II - staggered
Error in AA The graphs for type II and III are
switched
Concept Graph
13
Parabolic band diagram
integral
Linear electric field
integral
Constant charge density
4 most important concepts in EE
14
A prototype homojunction (a) The physical
diagram (b) the distribution of charge (c) the
electric field, obtained by integrating the
charge (d) the voltage, obtained by integrating
the field (e) the energy band diagram, with the
same shape as the voltage but inverted. Figure
5.11
p-n junction
n-p junction
Common mistake 1 direction or sign of E
field Common mistake 2 difference between
electrostatic potential V and electron energy (E
-qV) on (electron) band diagram Challenge what
is V and E for holes for the n-p junction on the
right?
15
P-i-n junction
Neutral p-region
Neutral n-region
i-region
n-p junction
Q
e
E
16
Band diagrams at equilibrium or non-equilibrium

• Constructing band diagrams from Electron Affinity
  Model (EAM)
• Very very useful for equilibrium cases (Fermi
  level is flat throughout)
• Constructing band diagrams from charge
  distribution
• Very very useful for non-equilibrium (Fermi level
  is NOT flat througout)
• For example, at threshold condition and flat band
  condition.

17
Band diagrams at equilibrium

• Constructing band diagrams from Electron Affinity
  Model (EAM)
• Very very useful for equilibrium cases (Fermi
  level is flat throughout)

18
The most essential concept in semiconductor
devices is B.D., B.D., B.D. (BD band diagram)

• Golden rules in constructing a band diagram at
  equilibrium using EAM
• Always start with the charge neutral band diagram
  (put it on the side)
• Fermi level is flat
• All other energy levels relative to EF in the
  bulk semiconductor (far from the interface) are
  the same
• Energy levels (EC and EV) at the interface do not
  change their relations
• Slopes of band bending (e (1/q) (dE/dx) ) at the
  interface related to dielectric constants ?1 ?2
  (?1 e1 ?2 e2 )

Concept Graph
19
Band diagrams at non-equilibrium (quasi-fermi
levels)

• Always construct band diagrams at equilibrium
  first
• Constructing band diagrams from charge
  distribution
• Very very useful for voltage-controlling devices
  (Fermi level is NOT flat througout)
• For example, in MOSFETs, at threshold condition
  and flat band condition, where you know the
  charge distribution!
• Constructing band diagrams from bias condition
• Very very useful for current-controlling devices
• For example, bipolar transistors or LEDs under
  known bias conditions (i.e. quasi-fermi level
  separation is known)

20
The most essential fundamentals in electrical
engineering Q, e, V, E
DP on parallel plate capacitors
Variation on parallel plate capacitors
Q
Q
E-field
E-field
V
V
qVbi - qVa
qVbi - qVa
(electron) Energy
(electron) Energy
21
Quasi Fermi-level

• Illustration of minority carrier diffusion in a
  surface-illuminated p-type semiconductor. The
  absorption is assumed to occur at the surface.
• Plots of the excess minority carrier
  concentration as a function of distance into the
  bar with increasing time. As the excess carriers
  are generated at the surface, they diffuse to
  regions of lower concentration, where they
  recombine.
• Figure 3.22

Illustration of quasi Fermi levels for electrons
and holes for the steady-state nonequilibrium
case of Figure 3.22, with e 0. Figure 3.24
Quasi Fermi-level tool to compute carrier
concentration at non-equilibrium
Concept Graph
22
Quasi Fermi-level
At equilibrium, Fermi level is flat and this ONE
Fermi level describes statistics of all particle
At non-equilibrium, every particle has its own
quasi Fermi-level
Equations
23
Quasi Fermi-level in forward biased p-n junction?
(DP question)

• Injecting minority carriers by
• Optical excitation
• Electric bias

Fig. 3.24
p
n
24
Quasi Fermi-level in forward biased p-n junction
n
p
Concept Graph
25
Quasi Fermi-level in forward biased p-n junction
? excess carriers exist in and near the depletion
region
For non-degenerate semiconductors
Equations
26
Quasi Fermi-level in reverse biased p-n junction
Concept Graph
27

• Outline
• Semiconductor properties
• Band diagrams
• P-n junctions, Schottky junctions and Ohmic
  contacts
• MOS junctions and FETs
• Bipolar transistors
• Optoelectronic devices
• Almost every slide describes a concept, or graphs
  equations associated with this concept. (C-G-E
  learning)

28
A prototype homojunction (a) The physical
diagram (b) the distribution of charge (c) the
electric field, obtained by integrating the
charge (d) the voltage, obtained by integrating
the field (e) the energy band diagram, with the
same shape as the voltage but inverted. Figure
5.11
p-n junction
n-p junction (Anderson-Anderson)
Depletion regions
This one is (electron energy) band diagram
Concept Graph
29
The pn homojunction under reverse bias. Solid
line equilibrium energy band diagram dashed
line energy band diagram under reverse bias. The
field increases this requires more ionized
acceptors and donors, so the depletion region
gets wider under reverse bias. Figure 5.6
Junction voltage
Junction voltage at equilibrium Vbi
At equilibrium, Ef is flat!
30
The space charge region width under equilibrium
and forward bias, and the corresponding energy
band diagrams. The depletion width decreases
under forward bias. Figure 5.7
Junction voltage
31

• Knowns ND, NA, ni, Vbi, Vj
• Unknowns wn, wp
• Setup equations
• Charge neutrality
• Gausss law (Poisson equation)
• 3. Electric field vs. electric potential

Equations
32
How carrier concentrations on both sides of the
junction are related?
Equilibrium energy band diagram for a step
junction. Figure 5.14
Equations
33
Long diode ideal forward bias currents
Confused?
Jn,drift, max Jtotal supplies electrons that
recombine with holes in n-region (hole diffusion
current) and that are injected over to the
p-side (electron diffusion current) Jp,drift,
max Jtotal supplies holes that recombine with
electrons in p-region (electron diffusion
current) and that are injected over to the
n-side (hole diffusion current)
34
Illustration of the diffusion current in a pn
junction in which the quasi-neutral region WB is
much shorter than an electron diffusion
length. Figure 5.19
Short diode ideal forward bias currents
35
Reverse-biased proptotype junction. The minority
carriers generated within the quasi-neutral
regions diffuse to the junction and contribute to
the reverse current. Diffusion current Figure
5.18
Diode ideal reverse bias currents
For an ideal diode, the junction current can be
described by diffusion currents at both forward
and reverse bias.
36
Illustration of the diffusion current and
generation current in a reverse-based pn
junction. The generation current is normally much
larger than the diffusion current. Figure 5.20
Deviation from ideal diode theory generation
and recombination current
Diode Non-ideal reverse bias current
generation current
Concept Graph
37
Diffusion current and recombination current in a
forward-biased pn junction. The barrier for
diffusion current is q(Vbi - Va). The barrier for
recombination current is about half that
value. Figure 5.21 Deviation from ideal diode
theory generation and recombination current
Diode Non-ideal forward bias current
recombination current
Concept Graph
38
n ideality factor
39
The I-Va characteristics illustrating Zener
tunneling, carrier multiplication, and avalanche.
The reverse and forward characteristics are not
plotted on the same scale. Figure 5.25

• Two major breakdown (i.e. diode can no longer
  block reverse bias) mechanisms
• Zener tunneling
• Avalanche

Forward bias
Reverse bias
Concept Graph
40
(a) A pn junction with dc voltage Va and ac
voltage Va applied. The resulting dc and ac
currents are I and i. (b) Small-signal
equivalent circuit for a pn junction indicating
the series resistance RS (of the contacts
and quasi-neutral regions, here lumped together
into one resistance), the junction resistance RP,
the junction capacitance Cj, and the
stored-charge capacitance Csc. The arrows
indicate that the parameters change with applied
voltage. Figure 5.29
Concept Graph
41
The small-signal resistance RP 1/GP is used to
find the output current variation for an input
voltage variation. Figure 5.30
Differential resistance (small signal resistance)
RP
Looks familiar? Emitter resistance in BJTs
(circuit class)
Equations
42
Illustration of the junction capacitance Cj. A
change in applied voltage Va produces a change in
the number of uncompensated ions on either side
of the junction. This produces a change in charge
dQ on either side of the junction, making the
junction look like a parallel-plate capacitor of
width w. Figure 5.31
Differential junction capacitance (small signal
capacitance) - dominates at reverse bias
Depletion region
Equations
43
Illustration of the stored-charge capacitance in
an np junction. (a) As the forward bias changes,
the number of injected electrons (minority
carriers) changes. In a one-sided junction the
hole injection is negligible. (b) An abrupt
decrease in the forward voltage DVa causes some
of the injected (stored) electrons to return to
the n side of the junction and contribute to
capacitance. Figure 5.33
Also called diffusion capacitance - dominates at
forward bias
Concept Graph
44
The circuit used to illustrate switching turn-off
and turn-on transients in a pn junction. Figure
5.34
Decay of injected electron concentration with
time after switching from VF to VR. Figure 5.35

• Reclaim minority carriers CSC
• Adjust depletion width Cj

Unfinished business in textbook
Concept Graph
45
The waveform resulting from a diode switched on
and off. (a) The input waveform (b) the diode
current (c) the diode voltage. The turn-off time
exceeds the turn-on time significantly. Figure
5.38
Switching speed determined by turn-off time
46
Quick note on diode current - I
47
Quick note on diode current - II
Charge control method calculation of diode
current (in comparison with charge diffusion
method)
48
Comparison of the I-Va characteristics of a
Schottky diode and a pn junction diode. The scale
for the reverse characteristic is compressed
compared with the scale for forward bias. Figure
6.22

• Key words for Schottky diodes
• Thermionic emission current
• Majority carrier device
• (i.e. electrons carry current in an n-
  Schottky, holes in p-Schottky)

49
A Schottky barrier diode made with a p-type
semiconductor. (a) Equilibrium (b) forward bias
(c) reverse bias. Figure 6.21
Error in A A P.335, bottom equation in the
exponential term, Eg(0) should be EB(0).
50
Low-resistance metal-semiconductor contacts using
degenerate surface layers. Metal-nn contact (a)
and metal-pp contact (b). The Schottky barrier
is thin enough to permit tunneling. Figure 6.23
Ohmic contacts almost all realistic ohmic
contacts are made in this fashion
51
Schottky contact
52
Schottky contact
53
Ohmic contact to n-type
Ohmic contact to p-type
54

• Outline
• Semiconductor properties
• Band diagrams
• P-n junctions, Schottky junctions and Ohmic
  contacts
• MOS junctions and FETs
• Bipolar transistors
• Optoelectronic devices
• Almost every slide describes a concept, or graphs
  equations associated with this concept. (C-G-E
  learning)

55
Field effect transistors Voltage controlled
barrier for current flow Input current (DC) zero
Capacitive actions Need two plates of charges
separated by an insulating layer
Choices of insulating layer oxide and depletion
region
Compare with current controlled barrier devices -
BJTs
56
The MOS capacitor. (a) Physical structure of an
n-Si/SiO2/p-Si MOS capacitor (b) cross section
(c) the energy band diagram under charge
neutrality (d) the energy band diagram at
equilibrium (note that the surface of the p-type
substrate near the oxide interface has become
weakly inverted). Figure 7.1
n -i p! Charge, field, potential, band
diagram?
Graph-concept
57
The MOS capacitor. (c) the energy band diagram
under charge neutrality (d) the energy band
diagram at equilibrium (note that the surface of
the p-type substrate near the oxide interface has
become weakly inverted). Figure 7.1
Surface band bending FS qfs and surface
potential fs
Surface potential
Equation
58
(a) Cross section of an n-channel FET (b) the
energy band diagram at equilibrium. Figure 7.5
At equilibrium, the channel charge accumulates in
the bulk near the oxide interface. In this case
the channel charge consists of electrons. Figure
7.6 Those electrons are in equilibrium with the
n ohmic region, being supplied from ohmic
contacts ? high f C-V is the same with low f C-V
curve!
59
(a) Circuit for measuring the capacitance of a
n-Si/SiO2/p Si capacitor MOS capacitor. (b)
Capacitance-voltage characteristic for a MOS
capacitor at low and high frequencies. Figure 7.3
Flat band (fs0)
Threhold (fs2ff)
Electrons in the inverted channel are generated
by slow process - thermal generation ? they do
not have enough time to appear in the channel
when subjected to a high frequency voltage change
Graph-concept
60
(a) Circuit for measuring the capacitance of gate
capacitor of a n-channel MOS transistor. (b)
Capacitance-voltage characteristic for a MOS
transistor gate capacitor at low and high
frequencies.
Electrons in the channel are supplied from n
ohmic contacts - Very fast process!
Graph-concept
Given this C-V graph, can you calculate the oxide
thickness?
61
The band bending at the surface of the
semiconductor. At threshold, the Fermi level is
as far above the intrinsic level at the surface
(left-hand edge) as it is below the intrinsic
level in the bulk. Figure 7.9
Below threshold, no conducting channel Above
threshold, conducting channel
Graph-concept - nMOSFET
62
The energy band diagram of the NFET across the
channel (a) and along the channel (b), with zero
voltage between the drain and the source. Figure
7.12
3. To pull down this barrier, we need apply a
positive bias on the gate
1. This barrier height controls how many
electrons in the channel
2. To form a conducting channel, we need pull
down this barrier
63
Inaccuracy the slope of Evac should be 1/3
smaller in Si than in SiO2
Evac
Threshold Condition I (fs2ff)
Induced mobile charges (electrons in this
example) ltlt ionized dopants (acceptors here) ?
Can be ignored
QB(2ff)
Area enclosed by e is VbiVT not Vbi!
Concept-Graph-Equation
64
Evac
q(2ff)
q(VTVbi)
Threshold Condition II (Still true fs2ff)
qfox
FS
Fm
Positive oxide charges or interfacial
charges ? Smaller charger at the gate ? Smaller
field inside the oxide ? Smaller total band
bending in Evac
QB(2ff)
Concept-Graph-Equation
Area enclosed by e is VbiVT not Vbi!
Donor-like traps Neutral when filled and
Positive when empty
65
Flatband Condition (fs 0)
Evac
Can you reason for VFB then?
QB0
Concept-Graph-Equation
Area enclosed by e is VbiVFB not Vbi!
66
The difference between high f and low f is true
for MOS (gate-back ohmic contact) capacitors
Oxide thickness
Doping in the semiconductor
However, there is no difference between high f
and low f for MOS (gate-S/D ohmic contact)
capacitors (since charges are supplied from the
top ohmic contacts)
Error in textbook, Figure S3.13
67
Long channel FET model with constant
mobility Saturation current
VS 0, VG 1 V, VD 2 V, VT 0.5 V
VG-Ch at source end ? VG-Ch at drain end ?
1 - 0 1 V gt 0.5 V
1 - 2 -1 V lt 0.5 V

• Why current saturates?
• E-field near the source is saturating
• Channel is pinching off (n ? 0) near the drain

68
The ID-VDS characteristics of a typical MOSFET.
The threshold voltage for this MOSFET is 0.5 V.
Figure 7.14
Feature 1 threshold voltage lt 0.5 V
Feature 2 the current saturates (J
qnv)? Since n is determined by VGS, it must be
due to v.
Reason 1 saturation velocity of carriers (short
channel)
Reason 2 electric field at the source end
saturates (long channel)
Concept-Graph
69
Long-channel MOSFET model with constant mobility
(Lgt 5mm) Step 1 calculate the channel charge
velocity
70
Long-channel MOSFET model with constant mobility
(Lgt 5mm) Step 2 calculate the channel charge
density Qch 0, VGS VT, ? ID 0 Qch ?,
VGS gt VT. Recall C-V of a MOSFET
Can you locate threshold condition (VT) from the
C-V below?
Above VT, Qch is determined by the gate oxide
capacitor
VT
71
Long channel FET model with constant
mobility Step3 solve for current by solving 1st
order differential equation
72
The ID-VDS characteristics of the NFET of Example
7.2 results from the simple model. For this
device W/L 5, tox 4 nm, Cox 8.63 10-3
F/m2, and mn 500 cm2/Vs. Figure 7.19
Non even spacing or even spacing? Square law or
linear law model Long channel or short?
73
Deviations from ideal I-Vs Channel length
modulation ? finite output conductance (ideally
zero)
Experimental ID-VDS characteristics for an
n-channel MOSFET for three values of gate
voltage. The current actually increases with
increasing VD in the current saturation region
because of channel-length modulation. For this
device, tox 4.7 nm, L 0.27 mm, W 8.6 mm,
and VT 0.3 V. Figure 7.21
Concept
74
Deviations from ideal I-Vs Transverse e-field ?
reduced carrier mobility
The effect of the transverse electric field on
the mobility. (a) The electrons in the channel
collide with the walls of the channel. (b) The
energy band diagram shows that the walls are
potential barriers at the oxide interface and the
barrier of the depletion region in the
semiconductor is sloped. Figure 7.24
Concept
75
Deviations from ideal I-Vs Lateral e-field ?
reduced carrier mobility
Channel electron mobility and velocity (v me)
as a function of lateral field for VGS 1.42
V. Figure 7.29
Concept-Graph-Equation
76
Deviations from ideal I-Vs Parasitic resistance
? reduced voltage drop across the intrinsic device
Schematic of an NMOS indicating the channel
resistance Rch, the source resistance RS, and the
drain resistance RD. Figure 7.33
77
Determine VT and m from MOSFET I-V
MOSFET ID-VGS characteristics measured
experimentally at VDS 0.1 V. The data are
plotted on a linear plot. The dashed line shows
the extrapolation of the curve at its point of
highest slope to the horizontal axis. The
extrapolation intersects the VGS axis at the
value VT VDS/2. The slope can be used to find
m0 and the deviation of the data from the
straight line can be used to find q. Figure 8.1
If VDS is small
If VGS is small
78
Subthreshold swing
The same ID-VGS characteristics from Figure 8.1,
but this time presented on a semilog plot. The
current varies approximately exponentially with
VGS below threshold. Figure 8.2
For logic circuit, choose VT 0.2 VDD The
steeper the subthreshold swing S, the smaller VDD
thus smaller power dissipation during
switching. Power dissipation subthreshold
leakage (static) switching (charging
pass-through currents dynamic dissipation)
How steep is good enough? What is the voltage
needed to change the current by 10 times (one
decade)
0.3 V over 4 decades ? 75 mV/decade
Concept-Graph
79
The capaciticances of the MOSFET gate oxide and
substrate. The substrate capacitance CB is the
depletion layer capacitance. Figure 8.3
Change EB
How is this related to high k gate dielectric
research?
Equation
80
(a) CMOS logic inverter circuit diagram (b)
input and output waveforms (c) the transfer
characteristics of a CMOS inverter. Figure 8.5
VTPMOS -2V VTNMOS 2V
5V
Both FETs have channels! ? current ? power
dissipation
Vin 2.5 V
81
(a) The inverter circuit (b) the input and
output signals. The solid line is the input
waveform the dashed line is the output. The
output cannot change instantaneously because it
requires some time for the load capacitance to
charge and discharge. (c) The charging and
discharging current that flows during a cycle.
One pulse flows through the n-channel device, the
other pulse flows through the p-channel
device. Figure 8.8
Charge CL
Discharge CL
Consequence of load capacitor gate delay and
power dissipation
82
(a) The inverter circuit (b) the input and
output signals. The solid line is the input
waveform the dashed line is the output. The
output cannot change instantaneously because it
requires some time for the load capacitance to
charge and discharge. (c) The charging and
discharging current that flows during a cycle.
One pulse flows through the n-channel device, the
other pulse flows through the p-channel
device. Figure 8.8
Dynamic power dissipation charge discharge
load
83
The current in the NFET as the input is switched
from a logic high to a logic low. Initially the
NFET output (drain) is high (point 1). When the
input is switched, the NFET turns on and current
can flow (point 2). The flowing current IDn
discharges the load capacitance (point 3),
sending the output voltage to zero (point
4). Figure 8.9
Propagation (gate) delay
84
Equivalent small-signal equivalent circuit for a
MOSFET (a) at high frequencies (b) neglecting
the source and drain resistances (c) at low
frequencies. Figure 8.13
gm
gd
Concept-Graph
85
Short channel effects Channel length modulation
Drain induced barrier lowering - DIBL
Illustration of the depletion regions between the
source and the substrate, and between the drain
and the substrate (a) for VDS 0. The effective
channel length L is reduced from that of the
metallurgical channel length Lm. (b) The EC y
diagram along the channel for VDS 0. (c) With
increasing VDS, the effective channel length L
decreases. Figure 8.17
(a) For long channels the drain voltage has
negligible effect on the barrier at the
source-channel interface. (b) For short-channel
devices the drain voltage tends to reduce the
barrier at the source end. (c) The result is
that the threshold voltage is decreased. The
effect is more pronounced as the channels get
shorter. Figure 8.19
86
The difference between long- and short-channel
behavior depends on the oxide thickness tox, the
source and drain junction depth xj, and the
depletion region thickness at the source, wS, and
drain, wD. Figure 8.20
To avoid short-channel effect (meaning weak
control over the channel by the gate), we have to
keep a right aspect ratio l/a!
87

• Outline
• Semiconductor properties
• Band diagrams
• P-n junctions, Schottky junctions and Ohmic
  contacts
• MOS junctions and FETs
• Bipolar transistors
• Optoelectronic devices
• Almost every slide describes a concept, or graphs
  equations associated with this concept. (C-G-E
  learning)

88

• A cut along the current path from emitter to
  collector for the npn device of Figure 9.1.
• The equilibrium
• energy band diagram for a BJT with
  uniform doping in each region.
• (c) The energy band diagram for
• operation in the active mode.
• Figure 9.2

One error in BD at equilibrium
Missing depletion region in the collector
BD under bias Fermi level in the quasi-neutral
region stays the same
qVR
qVR (Efp is above Efn)
qVF (Efn is above Efp)
89
Schematic indicating the relative magnitudes (not
to scale) of the various current components in an
npn BJT operating in the active mode.
Figure 9.3
95 electrons injected into the base - 1
recombines with holes from the p-base contact
- 94 goes to the collector becoming collector
current
100 electrons injected from emitter contact -
5 recombine with holes in the emitter injected
from the p-base - 95 injected into the p-base
i.e. 5 are hole diffusion current (IpE) 95
are electron diffusion current (InE) 100
are total emitter current (IE)
i.e. 1 is base recombination current (Irec)
94 are collector current (InC)
Let us see some simulations at this website
http//jas.eng.buffalo.edu/
Concept-Graph
90
E-B forward biased B-C zero biased
91
(a) The common emitter circuit with the dc
(capital letters) and small-signal, or ac,
quantities indicated (b) illustration of
operation along the load line. For IB 15 mA,
the dc operating point is at IC 2.2 mA and VCE
2.5 V. Figure 10.3a-b
92
Charge control model (not included in your
textbook)
93
E-B forward biased B-C zero biased
E-B forward biased B-C reverse biased
E-B forward biased B-C forward biased
94
Doping profile of a graded-base transistor. The
base doping profile as a function of position x
is approximated as a straight line in this
semilog plot, indicating an exponential impurity
distribution (and thus a constant electric field)
in the base. Figure 9.10
Graded Base ? quasi electric field! ? electrons
drift (diffuse) through the base!
Linear in log-linear plot (doping concentration -
position)
Reduce of electrons stored in the base ?
reduce Irec ? increase gain! ? reduce base
transit time ? faster speed!
Concept-Graph-Equation
95
The frequency response of a BJT, showing the
cutoff frequency fco (better referred as f-3dB ,
the -3dB point or the knee frequency) and the
unity gain frequency fT. Figure 10.10
96
Total delay td capacitance charging time
base delay collector delayUnity current gain
frequency fT 1/2ptd

• we will show one of the rc charging time is
  actually related to the base delay
• And the collector delay is related to the
  base-collector depletion width and the carrier
  saturation velocity
• Upper limit of fT can be estimated if we can
  eliminate all the parasitic resistances and
  capacitances

For example, WB0.1 um, DnB20 cm2s-1, ?
tB,transit 2.5 ps WBC0.2 um, vSAT 1e7 cms-1,
? tC,transit 1 ps
Correction in Eq. (10.50)
97
With increasing T
ex
1
Si BJTs
HBTs
98
Current crowding in a BJT. There is a voltage
drop across the base resistance RB, which varies
the emitter- base junction bias along the edge of
the emitter. The effect is a greater bias at the
end toward the base contact, and thus greater
base-emitter current flow at that end. Figure
9.15
I
For single side base electrode configuration,
the base resistance can be calculated to be
99
At a fixed IB, VBE is fixed after IC saturates.
Since VCE VBE VBC, VBC increases, thus
--- Early Effect
Punch-through or Avalanche breakdown
Kirk Effect
High injection effect (Webster)
Secondary effects in BJTs and their origins
100
Comparison of MOSFETs and BJTs
Band diagram along current flow direction
101
Comparison of MOSFETs and BJTs
102
Comparison of MOSFETs and BJTs
103

• Outline
• Semiconductor properties
• Band diagrams
• P-n junctions, Schottky junctions and Ohmic
  contacts
• MOS junctions and FETs
• Bipolar transistors
• Optoelectronic devices
• Almost every slide describes a concept, or graphs
  equations associated with this concept. (C-G-E
  learning)

104
Energy band diagram of the semiconductor of
Figure 3.18, under electrical bias and optical
illumination. The combination rate R, thermal
generation rate Gth, and the optical generation
rate Gop are illustrated. Figure 3.19
Eqn. 3.70

• Resistance changes with optical illumination
  intensity
• ? Photodetectors based on photo conductivity

Photoconductor
105
Light emitting diode
Photo diode (detector)
Solar cell
106
Any carrier flow at zero bias?
A generic photodiode (photodetector). Figure 11.2
Electron diffusion current
Electron drift current
Hole diffusion current
Hole drift current
Completely cancel each other gt I 0
p n
Current flowing direction same with reverse
bias current
107

• Important parameters
• For photodetectors responsivity
• For all optoelectronic devices quantum
  efficiency

108
How about the 4th quadrant?
Solar cell! Power dissipation in solar cell
(-I)(V) lt 0 ? Generating power!
Junction reverse biased
Junction forward biased. ? What happened to
the junction forward bias current?
109
The I-Va characteristic of a solar cell. The
maximum power is obtained at Pm ImVm. Figure
11.7
Important figures of merit for solar cells
How to maximize the conversion efficiency?
Maximize the fill factor ? obtain a more square
I-V (next slide) Maximize ISC ? maximize
absorption of photon and separation of electrons
and holes generated Maximize VOC ? increase Vbi
(limited by the bandgap of semiconductors for
homojunctions)
110
Review p-n junction BDs

• Note the potential/energy differences under
  difference bias
• Note the carrier distribution in the entire p-n
  junction under difference bias
• Note the difference in the junction voltage
  (Vbi-Va) and the applied voltage to the junction
  (Va)
• Va has signs ( for forward bias and for
  reverse bias)
• Recombination takes place in where Efn-Efp gt 0
  (or np gt ni2), i.e. 3 regions depletion region
  and one diffusion length from the depletion edge
  on both sides.

111
(a) The electrons injected into the p region
under forward bias must cross the plane x xn.
(b) Similarly, the holes injected into the n
region must also cross the plane x xp. (c) The
total current in the junction (neglecting
recombination current) is the sum of the two.
Outside the junction, the minority diffusion
currents decrease and the majority carrier drift
current increases to keep the total current
constant. Figure 5.17

• These injected minority carriers (diffusion
  current) eventually recombine with majority
  carrier ? photons and phonons

• But the emitted photons can be re-absorbed in a
  p-n homojunction, and the non-radiative processes
  (phonons) are competing with radiative processes
  (photons). What do we do?

• Let us 1) emit a photon with a smaller energy
  and 2) make the radiative recombination rate much
  higher!!

Long diode ideal forward bias currents
Concept Graph
112
Let us first take a look at the recombination
rate R
Most attractive region
Equations
113
Next, let us see how to emit a photon with a
smaller energy
Straddling is preferred since it confines both
electrons and holes
It makes sense to insert a smaller bandgap
material here. Type I, II, or III?
114
(a) A double-heterostructure LED pn diode. The
potential wells for electrons and holes capture
carriers and increase the probability of
recombination. (b) The E-K diagram reminds us
that K must also be conserved. Thus LEDs are
usually made from direct-gap materials. Figure
11.12
Let us also check with the rules of the thumb of
photon emission

• Both energy and momentum have to be conserved!

• Electrons and holes have to be close in
• both real space and k-space to emit photons!

K (2p/l) of a photon is very small compared to
the crystal momentum K
115
The power-current curve of a laser diode. Below
threshold, the diode is an LED. Above threshold,
the population is inverted and the light output
increases rapidly. Figure 11.24
Difference between LED and LD (gain feedback)
Gain lt loss
Gain loss
Gain gt loss
116
Efn-EfpgtEg
No! Lots of electrons, but few holes!
SB
Concept-Graph
Population inversion
117
Development of lasing. (a) The gain distribution
is the same as the spontaneous emission spectrum.
(b) Only the photons at the resonance will
amplify. The ones near the center of the gain
curve will amplify the fastest. Figure 11.28
E.g. l630 nm d100 mm n 3.2 ?Dl0.62 nm Many
modes
Concept-Graph-Equation