etae pat packet switches

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?eta???e?? pa??t??(packet switches)

• Input versus output queueing (knockout switch)
• ?pt???? ??µß?? µeta????? pa??t??
• The Scheduling Switch
• Virtual Circuit Deflection routing
• Multistage Interconnection Network switches (MIN
  switches)

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Crossbar µeta????a? µe buffers st?? e?s?d???

? e?s?d??, ? ???d?? (?3 st? s??µa) ? ??????
?????eta? se s??sµ?? (t? p??? ??a pa??t?
ft??e? se ???e e?s?d? a?? s??sµ?) ?a pa??ta (p?
ATM cells) ????? ?s? µ???? ?p?????? buffers µ???
st?? e?s?d???. ???ß??µa Head of Line (HOL)
blocking ?p??e? ?a ap?de??te? ?t? Maximum
throughput 0.58
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?eta????a? Knockout
Concentrator e??? knockout switch

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All-Optical Packet Switching
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?pt???? µeta????a? pa??t?? d?aµ???a??µe???
µ??µ?? (Shared Memory Optical Packet Switch -
SMOP)

• Recirculating-loop µ??µ? µe ?????d??µ?????s?.
• ?e? e??a? modular.

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? Staggering µeta????a?

• ???s?µ????e? ??a µeta????a µe buffers e??d??
  ß????? b.
• ?? p????? t?? ??aµµ?? ?a??st???s?? µe?a???e?
  ??aµµ??? µe t? ß???? t?? buffers.
• ??s? µe???? p??pe? ?a ???e? t? b ??a
  ?ata???st??? ?????f???a
• ?p?s?? de? e??a? modular

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?eta????a? µe µe?????? ?pt????? buffers (Switch
with Large Optical Buffers - SLOB)
a???s?µ?p???ta
e?s?d??
???d??

• ????? buffer t?? bk-1 pa??t??, ?p?? k t? p?????
  t?? ep?p?d??.
• Modular s?ed?asµ??.

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The Scheduling Switch

• Objectives
• lossless communication
• efficient utilization of the capacity
• processing times that are optimal in terms of
  operations per
• packet through batch processing of headers
• consistency with label and virtual circuit
  switching
• packet arrival in the correct order
• modularity of the design
• cost that is optimal or near-optimal (as
  measured by the
• number of elementary crosspoints)
• nonblocking design
• suitability not only for optical packet
  switching but for
• circuit switching as well
• transparency at the payload bit rate

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?eta????a? ?????d??µ?????s?? (Scheduling Switch)

• ?a pa??ta a?ad?at?ss??ta? ap? t?? scheduler ?ts?
  ?ste ta pa??ta p?? eµfa?????ta? ?at? t? d????e?a
  t?? ?d?a? s??sµ?? st?? e??d??? t?? scheduler ?a
  apa?t??? d?af??et????? e?e???µe???? s??d?sµ???
  t?? crossbar.
• ? se??? t?? pa??t?? d?at??e?ta? ??a ??a ded?µ???
  ?e???? e?s?d??-e??d??.

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The Scheduling Switch
T packet slots
incoming link i
Scheduling Switch
outgoing link j
incoming link l
incoming link k

• ? s???d?? e??a? (n,T)-smooth, a? µp??e? ?a
  µetad?se? t? p??? n pa??ta se ??a p?a?s?? (frame)
  µe?????? T (? µ?s?? ???µ?? e??a? nC/T). ??t? ?
  ?d??t?ta d?at??e?ta? ?a? st??? a?????????
  s??d?sµ???.
• ?s? µe?a??te?? e??a? t? T,
• a. t?s? p?? ?ata???st??? ep?t??peta? ?a e??a? ?
  s???d??.
• ß. t?s? µe?a??te?? e??a? ? e?e????a st?? a???es?
  ???µ??.
• ?. ??s? pe??ss?te?e? ??aµµ?? ?a??st???s??
  ??e?a??µaste.
• G?a ???e s??desµ? p??pe? ?a e?asfa???eta?, ?t?

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• nij a???µ?? pa??t?? p?? ft????? st?? e?s?d? i
  ?a? p????????ta? ??a t?? ???d? j st?? d????e?a
  e??? p?a?s??? (frame)
• ??????µe Nnij frame matrix
• Critical sum h of a matrix max. of row sums and
  column sums.
• G?a t?? frame matrix ?s??e? hT.
• ??t? s??ep??eta? ?t?
• ?Si1T Pi,
• ?p?? ?? Pi e??a? permutation matrices
• O Pi ?a?????e? ta pa??ta p?? eµfa?????ta? st??
  ???d? t?? scheduler st? slot i, ?a? e?asfa??????
  ?t? de? ?p?????? s??????se??

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?????d??µ?????t?? (Scheduler)
MlogT

• ???p??e?ta? µe N pa??????a ??ad?? (branches),
  ??a ??a ???e e?s?d?.
• ???e ??ad? ap?te?e?ta? ap? 2logT-1 µp???
  ?a??st???s??.

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Benes-?s?d??aµ? d??t??
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??d? p??t??????? ??a e??at?stas?? s??des?? ?a?
d?sµe?s? ????t???t?ta?
IRVC immediate reservation virtual circuit
protocol (??ass??? p??t?????? e??at?stas??
s??des?? ?a? d?sµe?s?? ????t???t?ta?). ERVC
efficient reservation virtual circuit protocol
(JET, Just in Time or Just Enough Time protocol
). ?esµe?e? ????t???t?ta µe ???s? ????????
??at?se?? (timed reservations) ?a? µe????t????
??at?se?? (advance reservations). RGVC
ready-to-go virtual circuit protocol. ??de????
pre-transmission delay. ?a?????? p???p???te? t??
?pa??? s?µa?t???? buffers st??? e?d??µes???
??µß???.

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ERVC efficient reservation virtual circuit
protocol

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???t?????? e???????? ?????µat??
e?t??p?? (Deflection Virtual Circuit Protocol)
G?a pe??pt?se?? ?p?? ????µe e????st? buffering
(?p?? sta p????? ?pt??? d??t?a), ?a? apa?te?ta?
µ?de???? ap??e?a pa??t??, ????? e? t?? p??t????
??at?se?? ?a? ap?? a?ad??ta?? (resequencing) t??
pa??t?? t?? p?????sµ?.
µ???p?t? t?? de?te??? block
set-up pa??ta
p??t?µ?µe?? µ???p?t?
p???
? s???d?? ?????eta?
µ???p?t? t?? p??t?? block
?? t? set-up pa??t? de? µp??e? ?a a???????se? t?
p??t?µ?µe?? µ???p?t?, ?ata?aµß??e? ??a? ????
e?e???µe?? s??desµ? (µe se??? p??t?µ?s??) ?a? ?
s???d?? e?t??peta?. ?? ?e?? a??µesa st? set-up
pa??t? ?a? st? p??t? pa??t? ded?µ???? p??pe? ?a
e??a? epa???? ??a H e??????? t?? p??????
d??µ?????s?? ?p?? H e??a? ??a ??? ???? st? µ????
t?? µ???pat???.
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??µß??
s??????? e?se???µe?? ????t???t?ta s???????
e?e???µe?? ????t???t?ta Ctotal
e?se???µe?? s???d??
d?a??s?µ? e?e???µe?? ????t???t?ta
??e???µe?? ????t???t?ta t??????st?? ?s? µe r
µp??e? p??ta ?a ß?e?e?, p??a??? µe t? ??st?? t??
d?a??p?? s???d?? p?? ????? p??? t?? A. ?? s???d??
p?? d?a??pt??ta?, s??e?????? t? µet?d?s? ?ta? ?
p??? ??ße? ??a µ???µa ap???????. ??a s???d??
µp??e? ?a ??e?aste? ?a ????ste? se k ?p?s???d???
(? a?ad??ta?? k µp??? pa??t?? e??a? e?????te??
ap? t?? a?ad??ta?? a?e???t?t?? pa??t??).
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Burst Switching Concept
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Multistage Interconnection Networks for building
high-speed switches
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Generalization of the
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