Activation Records (Introduction)

1
Activation Records(Introduction)

• Mooly Sagiv
• html//www.math.tau.ac.il/msagiv/courses/wcc03.ht
  ml
• Chapter 6.3

2
Outline

• What is the problem?
• A possible structure of the activation records
• A simple stack machine
• Example compilation

3
The problem

• The compiler needs to allocate memory for
  variables
• Consistent with program semantics
• Scope
• Duration
• Recursion
• Efficient (moderate runtime cost)
• Solution?

4
Typical Virtual Memory Content
static area
Stack area
Heap area
Lower addresses
5
A Typical Stack Frame
6
Basic Compiler Phases
7
Example Program
void main() printf(d\n, fact(3)) int
fact(int n) if (n0) return 1 else
return n fact(n-1)
8
Activation Record for main(before fact)
void main() printf(d\n, fact(3))
Administrative part 3
FP
SP
9
Activation Record for main(after fact)
void main() printf(d\n, fact(3))
Administrative part 3 6
FP
SP
10
Activation Record for main(before printf)
void main() printf(d\n, fact(3))
Administrative part 6 x87
FP
SP
d\n
x87
11
Stack Instructions
Instruction Actions
Push_Const c stack--SPc
Push_Local i stack--SPstackFPi
Store_Local i stackFPistackSP
Add_Top2 stackSP1stackSP
Sub_Top2 stackSP1-stackSP
Mul_Top2 stackSP1stackSP
Branch L PC L
Branch_Eq L T1 stackSP T2 stackSP if (T1T2) PC L
JSR L stack--SP FP stack--SP PC FPSP-1PC L
RTS T stackSP PCstackSP FPstackSP stack--SPT
WPop StackSP1 StackSP
12
Code Generated for main
.global _main L1 Push_Const 3
Push_Const 0 JSR _fact WPop
Push_Const L2 JSR _printf .data L2
d\n .end
void main() printf(d\n, fact(3))
13
Activation Record for fact
int fact(int n) if (n0) return 1 else
return n fact(n-1)
n
FP5
Administrative part
3
ret
0
FP
SP
14
Code generated for fact
L5 Push_Local 5 Push_Local 5
Push_Const 1 Subtr_Top 2
Push_Const 0 JSR _fact WPop
Mult_Top2 RTS
.global _fact L3 Push_Local 5
Push_Const 0 Branch_Eq L4
Branch L5
int fact(int n) if (n0) return 1 else
return n fact(n-1)
L4 Push_Constant 1 RTS
.end
15
Execution of fact
main
L3 Push_Local 5 Push_Const 0
Branch_Eq L4 Branch L5 L4
Push_Constant 1 RTS L5 Push_Local
5 Push_Local 5 Push_Const 1
Subtr_Top 2 Push_Const 0
JSR _fact WPop Mult_Top2
RTS
n
FP5
Administrative part
3
ret
0
FP
16
Execution of fact
L3 Push_Local 5 Push_Const 0
Branch_Eq L4 Branch L5 L4
Push_Constant 1 RTS L5 Push_Local
5 Push_Local 5 Push_Const 1
Subtr_Top 2 Push_Const 0 JSR
_fact WPop Mult_Top2 RTS
main
n
FP5
Administrative part
3
0
ret
FP
SP
3
17
Execution of fact
L3 Push_Local 5 Push_Const 0
Branch_Eq L4 Branch L5 L4
Push_Constant 1 RTS L5 Push_Local
5 Push_Local 5 Push_Const 1
Subtr_Top 2 Push_Const 0 JSR
_fact WPop Mult_Top2 RTS
main
n
FP5
Administrative part
3
ret
0
FP
3
0
18
Execution of fact
L3 Push_Local 5 Push_Const 0
Branch_Eq L4 Branch L5 L4
Push_Constant 1 RTS L5 Push_Local
5 Push_Local 5 Push_Const 1
Subtr_Top 2 Push_Const 0 JSR
_fact WPop Mult_Top2 RTS
main
n
FP5
Administrative part
3
ret
0
FP
19
Execution of fact
L3 Push_Local 5 Push_Const 0
Branch_Eq L4 Branch L5 L4
Push_Constant 1 RTS L5 Push_Local
5 Push_Local 5 Push_Const 1
Subtr_Top 2 Push_Const 0 JSR
_fact WPop Mult_Top2 RTS
main
n
FP5
Administrative part
3
ret
0
FP
20
Execution of fact
L3 Push_Local 5 Push_Const 0
Branch_Eq L4 Branch L5 L4
Push_Constant 1 RTS L5 Push_Local
5 Push_Local 5 Push_Const 1
Subtr_Top 2 Push_Const 0 JSR
_fact WPop Mult_Top2 RTS
main
n
FP5
Administrative part
3
ret
0
FP
3
21
Execution of fact
L3 Push_Local 5 Push_Const 0
Branch_Eq L4 Branch L5 L4
Push_Constant 1 RTS L5 Push_Local
5 Push_Local 5 Push_Const 1
Subtr_Top 2 Push_Const 0 JSR
_fact WPop Mult_Top2 RTS
main
n
FP5
Administrative part
3
ret
0
FP
3
3
22
Execution of fact
L3 Push_Local 5 Push_Const 0
Branch_Eq L4 Branch L5 L4
Push_Constant 1 RTS L5 Push_Local
5 Push_Local 5 Push_Const 1
Subtr_Top 2 Push_Const 0 JSR
_fact WPop Mult_Top2 RTS
main
n
FP5
Administrative part
3
ret
0
FP
3
3
1
23
Execution of fact
L3 Push_Local 5 Push_Const 0
Branch_Eq L4 Branch L5 L4
Push_Constant 1 RTS L5 Push_Local
5 Push_Local 5 Push_Const 1
Subtr_Top 2 Push_Const 0 JSR
_fact WPop Mult_Top2 RTS
main
n
FP5
Administrative part
3
ret
0
FP
3
2
24
Execution of fact
L3 Push_Local 5 Push_Const 0
Branch_Eq L4 Branch L5 L4
Push_Constant 1 RTS L5 Push_Local
5 Push_Local 5 Push_Const 1
Subtr_Top 2 Push_Const 0 JSR
_fact WPop Mult_Top2 RTS
main
n
FP5
Administrative part
3
ret
0
FP
3
2
0
25
main
L3 Push_Local 5 Push_Const 0
Branch_Eq L4 Branch L5 L4
Push_Constant 1 RTS L5 Push_Local
5 Push_Local 5 Push_Const 1
Subtr_Top 2 Push_Const 0 JSR
_fact WPop Mult_Top2 RTS
0
0
FP
1
n
0
ret
26
main
0
L3 Push_Local 5 Push_Const 0
Branch_Eq L4 Branch L5 L4
Push_Constant 1 RTS L5 Push_Local
5 Push_Local 5 Push_Const 1
Subtr_Top 2 Push_Const 0 JSR
_fact WPop Mult_Top2 RTS
0
1
n
0
ret
Administrative part 0
FP
1
27
main
FP
0
n
0
0
L3 Push_Local 5 Push_Const 0
Branch_Eq L4 Branch L5 L4
Push_Constant 1 RTS L5 Push_Local
5 Push_Local 5 Push_Const 1
Subtr_Top 2 Push_Const 0 JSR
_fact WPop Mult_Top2 RTS
ret
Administrative part
1
SP
1
n
0
ret
Administrative part
1
28
main
0
L3 Push_Local 5 Push_Const 0
Branch_Eq L4 Branch L5 L4
Push_Constant 1 RTS L5 Push_Local
5 Push_Local 5 Push_Const 1
Subtr_Top 2 Push_Const 0 JSR
_fact WPop Mult_Top2 RTS
0
1
n
0
ret
Administrative part 0 1
FP
1
SP
29
main
0
L3 Push_Local 5 Push_Const 0
Branch_Eq L4 Branch L5 L4
Push_Constant 1 RTS L5 Push_Local
5 Push_Local 5 Push_Const 1
Subtr_Top 2 JSR _fact
Push_Const 0 WPop Mult_Top2
RTS
1
n
0
ret
Administrative part 1
FP
1
30
main
0
L3 Push_Local 5 Push_Const 0
Branch_Eq L4 Branch L5 L4
Push_Constant 1 RTS L5 Push_Local
5 Push_Local 5 Push_Const 1
Subtr_Top 2 Push_Const 0 JSR
_fact WPop Mult_Top2 RTS
1
n
0
ret
Administrative part
FP
1
31
main
0
L3 Push_Local 5 Push_Const 0
Branch_Eq L4 Branch L5 L4
Push_Constant 1 RTS L5 Push_Local
5 Push_Local 5 Push_Const 1
Subtr_Top 2 Push_Const 0 JSR
_fact WPop Mult_Top2 RTS
0
FP
1 1
n
ret
32
main
0
L3 Push_Local 5 Push_Const 0
Branch_Eq L4 Branch L5 L4
Push_Constant 1 RTS L5 Push_Local
5 Push_Local 5 Push_Const 1
Subtr_Top 2 Push_Const 0 JSR
_fact WPop Mult_Top2 RTS
0
FP
1
n
33
main
0
L3 Push_Local 5 Push_Const 0
Branch_Eq L4 Branch L5 L4
Push_Constant 1 RTS L5 Push_Local
5 Push_Local 5 Push_Const 1
Subtr_Top 2 Push_Const 0 JSR
_fact WPop Mult_Top2 RTS
0
FP
34
main
0
L3 Push_Local 5 Push_Const 0
Branch_Eq L4 Branch L5 L4
Push_Constant 1 RTS L5 Push_Local
5 Push_Local 5 Push_Const 1
Subtr_Top 2 Push_Const 0 JSR
_fact WPop Mult_Top2 RTS
FP
2 2
n
ret
35
main
0
L3 Push_Local 5 Push_Const 0
Branch_Eq L4 Branch L5 L4
Push_Constant 1 RTS L5 Push_Local
5 Push_Local 5 Push_Const 1
Subtr_Top 2 Push_Const 0 JSR
_fact WPop Mult_Top2 RTS
FP
2
36
main
0
L3 Push_Local 5 Push_Const 0
Branch_Eq L4 Branch L5 L4
Push_Constant 1 RTS L5 Push_Local
5 Push_Local 5 Push_Const 1
Subtr_Top 2 Push_Const 0 JSR
_fact WPop Mult_Top2 RTS
FP
37
FP
main
L1 Push_Const 3 Push_Const 0
JSR _fact WPop Push_Const
L2 JSR _printf
3
n
6
ret
38
FP
main
L1 Push_Const 3 Push_Const 0
JSR _fact WPop Push_Const
L2 JSR _printf
6
39
FP
main
L1 Push_Const 3 Push_Const 0
JSR _fact WPop Push_Const
L2 JSR _printf
6
x87
40
main
_printf
6
x87
x87
FP
Administrative part
41
Code For Register Machine
42
Register Instructions
Instruction Actions
Load_Const c, Ri Ric
Load_Local c(Ri), Rj Rj(Ric)
Store_Local Ri, c(Rj) (Rjc)Ri
Add_Constant c, Ri Ri Ric
Add_Reg Ri, Rj Rj RjRi
Sub_Constant Ri, c Ri Ri - c
Sub_Reg Ri, Rj Rj Rj-Ri
CMP Ri, Rj CC Ri -Rj
CMP_Const C, Ri CC Ri - C
Branch L PC L
Branch_EQ L if (CCEQ) PC L
JSR L (--SP) FP (--SP) PC FPSP-1PC L
RTS PC(SP) FP(SP)
43
Register Code Generated for main
.global _main Add_Constant -K1, SP L1
Load_Const 3, R0 JSR _fact
Load_Reg R0, R1 Load_Const L2, R0
JSR _printf Add_Constant K1, SP
RTS .data L2 d\n .end
void main() printf(d\n, fact(3))
44
Register Code generated for fact
L5 Store_Local R0, 5(FP)
Sub_Constant 1, R0 JSR _fact
Load_Local 5(FP), R1 Mult_Reg R1, R0
Goto L6
.global _fact Add _Constant -K2, SP L3
Cmp_Constant R0, 0 Branch_Eq L4
Branch L5
int fact(int n) if (n0) return 1 else
return n fact(n-1)
L4 Load_Constant 1, R0 Goto L6
L6 Add_Constant K2, SP RTS .end
45
Summary

• Activation records is a runtime data structure
• Updated by code generated by the compiler
• Support from machine instruction