SHOBHA K'R

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MEALY SEQUENTIAL MACHINE
shobha_shankar_at_yahoo.com
SHOBHA K.R MSRIT
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DEFINITION OF A STATE MACHINE

• All programmable logic designs can be specified
  in Boolean form. However some designs are easier
  to conceptualize and implement using non-Boolean
  models. The State Machine model is one such
  model.

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DEFINITION OF A STATE MACHINE

• A state machine represents a system as a set of
  states, the transitions between them, along with
  the associated inputs and outputs.
• So, a state machine is a particular
  conceptualization of a particular sequential
  circuit. State machines can be used for many
  other things beyond logic design and computer
  architecture.

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FINITE STATE MACHINES

• Any circuit with memory is a finite state machine
• Even computers can be viewed as huge FSMs
• Design of FSMs involves
• Defining states
• Defining transitions between states
• Optimization / minimization
• Above approach is practical for small FSMs only

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STATE MACHINES DEFINITION OF TERMS

• Branch
• A change from present state to next state.
• Mealy Machine
• A state machine that determines its outputs from
  the present state and from the inputs.

• State Diagram
• Illustrates the form and function of a state
  machine. Usually drawn as a bubble-and-arrow
  diagram.
• State
• A uniquely identifiable set of values measured at
  various points in a digital system.
• Next State
• The state to which the state machine makes the
  next transition, determined by the inputs present
  when the device is clocked.

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PRESENT STATE AND NEXT STATE
For any given state, there is a finite number of
possible next states. On each clock cycle, the
state machine branches to the next state. One
of the possible next states becomes the new
present state, depending on the inputs present on
the clock cycle.

• On a well-drawn state diagram, all possible
  transitions will be visible, including loops back
  to the same state. From this diagram it can be
  deduced that if the present state is State 5,
  then the previous state was either State 4 or 5
  and the next state must be either 5, 6, or 7.

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MEALY MACHINE

• The Mealy State Machine generates outputs based
  on
• The Present State, and
• The Inputs to the M/c.
• So, it is capable of generating many different
  patterns of output signals for the same state,
  depending on the inputs present on the clock
  cycle.

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MEALY MACHINE

• Describe outputs as concurrent statements
  depending on state and inputs

transition condition 1 / output 1
transition condition 2 / output 2
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MEALY FSM EXAMPLE Bcd to excess 3 code converter
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MEALY FSM EXAMPLE
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MEALY FSM EXAMPLE STATE GRAPH
A
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MEALY FSM EXAMPLE
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SIMPLIFIED STATE TABLE
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MEALY FSM EXAMPLE
SIMPLIFIED STATE DIAGRAM
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MEALY FSM EXAMPLE
Guide lines for reducing the amount of logic
required

• I. States which have the same next state (NS) for
  a given input should be given adjacent
  assignments (look at the columns of the state
  table).
• II. States which are the next states of the same
  state should be given adjacent assignments(look
  at the rows).
• III. States which have the same output for a
  given input should be given adjacent assignments.

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MEALY FSM EXAMPLE
Assignment map
I. (1,2) (3,4) (5,6) (in the X1 column, S1 and
S2 both have NS S4in the X0 column, S3 S4
have NS S5, and S5 S6 have NS S0) II. (1,2)
(3,4) (5,6) (S1 S2 are NS of S0 S3 S4 are NS
of S1and S5 S6 are NS of S4) III. (0,1,4,6)
(2,3,5)
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MEALY FSM EXAMPLE
State table
Transition table
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MEALY FSM EXAMPLE
Excitation table
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MEALY FSM EXAMPLE
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REALIZATION OF CODE CONVERTER USING D F/F
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VHDL CODE FOR BCD TO EXCESS3 contd..
library ieee use ieee.std_logic_1164.all
entity SM1_2 is port(X, CLK in bit Z out
bit) end SM1_2 architecture Table of SM1_2
is signal State, Nextstate integer
0 begin process(State,X) --Combinational
Network begin case State is when 0 gt if X'0'
then Zlt'1' Nextstatelt1 end if if X'1' then
Zlt'0' Nextstatelt2 end if
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VHDL CODE FOR BCD TO EXCESS3 contd..
when 1 gt if X'0' then Zlt'1' Nextstatelt3 end
if if X'1' then Zlt'0' Nextstatelt4 end
if when 2 gt if X'0' then Zlt'0' Nextstatelt4
end if if X'1' then Zlt'1' Nextstatelt4 end
if when 3 gt if X'0' then Zlt'0' Nextstatelt5
end if if X'1' then Zlt'1' Nextstatelt5 end
if when 4 gt if X'0' then Zlt'1' Nextstatelt5
end if if X'1' then Zlt'0' Nextstatelt6 end
if
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VHDL CODE FOR BCD TO EXCESS3 contd..
when 5 gt if X'0' then Zlt'0' Nextstatelt0 end
if if X'1' then Zlt'1' Nextstatelt0 end
if when 6 gt if X'0' then Zlt'1' Nextstatelt0
end if when others gt null -- should not
occur end case end process process(CLK) --
State Register begin if CLK'1' then -- rising
edge of clock State lt Nextstate end if end
process end Table
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WAVEFORM FOR BCD TO EXCESS -3