Computer%20Architecture%20Notes%20Jan%2026,%202004

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Computer ArchitectureNotes Jan 26, 2004

• Dusan Kuzmanovic
• Jimmy Ortegon

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Machine Instruction Encoding
op
LOAD ltADDRgt
ltADDRgt
A
a
3
Three Address Format
15
0
op
ADD lt30gt, lt100gt, lt200gt
30
100
200
MEMORY
ALU
CPU
4
Two Address Format
op
LOAD R1, lt gt ADD lt gt, lt gt ADD R1, R2 ADD
lt30gt, lt100gt
30
100
MEMORY
ALU
CPU
5
One Address Format
op
ADD lt30gt
30
MEMORY
ALU
CPU
A
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Register to Register Format
2 Register
ADD ltR1gt, ltR2gt
op
R1
R2
Second Operand
First Operand
3 Register
ADD ltR1gt, ltR2gt, ltR3gt
op
R1
R2
R3
Result
Second Operand
First Operand
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Zero Address Architecture or Stack Architecture
SP Stack Memory
An stack memory
MEMORY
S T A C K

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Zero Address Architecture or Stack Architecture
REGISTER MEMORY LOAD R1,A ADD R2,R1,B STORE R3, C

• STACK
• PUSH A
• ADD
• POP C

ACUMMULATOR LOAD A ADD B STORE C
LOAD R1,A LOAD R2,B ADD R3,R2,R1 STORE R3
LOAD/ STORE
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Sun Sparc Load/ Store Architecture

• INTEL PENTIUM
• 2 ADDRESS FORMAT WITH OPERAND IN A REGISTER
  AND THE OTHER IN A REGISTER ON MEMORY

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Harvard Architecture Mark-I First Machine
DM Data Memory IM Instruction Memory
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Parallel Instruction Execution
PC
MAR 2
MAR 1
1
DM
IM
MULTIPLEXER
MDR 1
MDR 2
A
DECODER

OV
gt
lt

CONDITION CODES
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Fetch

• MAR1 ? PC
• MDR 1 ? IMMAR1 PC ? PC 1
• IR ? MDR 1
• DECODER ? IR.OP
• NOTE
• JMP depending on lt gt
• PC ? IR.ADDR

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Load

• MAR 2 ? IR.ADDR
• MDR 2 ? DMMAR 2
• A ? MDR 2

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Add

• MAR2 ? IR.ADDR MAR 1 ? PC
• MDR2 ? DMMAR 2 MDR?IMMAR 1
• A ? A MDR 2 IR ? MDR 1