week4-1

1

• Lecture 10
• Wire and Via
• Jan. 27, 2003

2
Topics

• Wire and via structures.
• Wire parasitics and resistance.
• Transistor parasitics and resistance.

3
Wires and vias
metal 3
metal 2
vias
metal 1
poly
poly
p-tub
n
n
4
Metal migration

• Current-carrying capacity of metal wire depends
  on cross-section. Height is fixed, so width
  determines current limit.
• Metal migration when current is too high,
  electron flow pushes around metal grains. Higher
  resistance increases metal migration, leading to
  destruction of wire.

5
Metal migration problems and solutions

• Marginal wires will fail after a small operating
  periodinfant mortality.
• Normal wires must be sized to accomodate maximum
  current flow
• Imax 1.5 mA/?m of metal width.
• Mainly applies to VDD/VSS lines.

6
Diffusion wire capacitance

• Capacitances formed by p-n junctions

sidewall capacitances
depletion region
n (ND)
bottomwall capacitance
substrate (NA)
7
Depletion region capacitance

• Zero-bias depletion capacitance
• Cj0 ?si/xd.
• Depletion region width
• xd0 sqrt(1/NA 1/ND)2?siVbi/q.
• Junction capacitance is function of voltage
  across junction
• Cj(Vr) Cj0/sqrt(1 Vr/Vbi)

8
Poly/metal wire capacitance

• Two components
• parallel plate
• fringe.

fringe
plate
9
Metal coupling capacitances

• Can couple to adjacent wires on same layer, wires
  on above/below layers

metal 2
metal 1
metal 1
10
Example parasitic capacitance measurement

• n-diffusion bottomwall2 fF, sidewall2 fF.
• metal plate0.15 fF,
  fringe0.72 fF.

1.5 ?m
3 ?m
0.75 ?m
2.5 ?m
1 ?m
11
Wire resistance

• Resistance of any size square is constant

12
Mean-time-to-failure

• MTF for metal wires time required for 50 of
  wires to fail.
• Depends on current density
• proportional to j-n e Q/kT
• j is current density
• n is constant between 1 and 3
• Q is diffusion activation energy

13
Skin effect

• At low frequencies, most of copper conductors
  cross section carries current.
• As frequency increases, current moves to skin of
  conductor.
• Back EMF induces counter-current in body of
  conductor.
• Skin effect most important at gigahertz
  frequencies.

14
Effect on resistance

• Low frequency resistance of wire
• Rdc 1/ s wt
• High frequency resistance with skin effect
• Rhf 1/2 s d (w t)
• Resistance per unit length
• Rac sqrt(Rdc 2 k Rhf 2)
• Typically k 1.2.

15
Review

• Current characteristics
• Capacitance
• Wire and via (tub tie)

16

• Lectures 11
• Design Rule and Stick Diagram
• Jan. 29, 2003

17
Topics

• Design rules and fabrication.
• Color codes and Stick diagrams.

18
Why we need design rules

• Masks are tooling for manufacturing.
• Manufacturing processes have inherent limitations
  in accuracy.
• Design rules specify geometry of masks which will
  provide reasonable yields.
• Design rules are determined by experience.

19
Manufacturing problems

• Photoresist shrinkage, tearing.
• Variations in material deposition.
• Variations in temperature.
• Variations in oxide thickness.
• Impurities.
• Variations between lots.
• Variations across a wafer.

20
Transistor problems

• Varaiations in threshold voltage
• oxide thickness
• ion implanatation
• poly variations.
• Changes in source/drain diffusion overlap.
• Variations in substrate.

21
Wiring problems

• Diffusion changes in doping -gt variations in
  resistance, capacitance.
• Poly, metal variations in height, width -gt
  variations in resistance, capacitance.
• Shorts and opens

22
Oxide problems

• Variations in height.
• Lack of planarity -gt step coverage.

metal 2
metal 1
metal 2
23
Via problems

• Via may not be cut all the way through.
• Undesize via has too much resistance.
• Via may be too large and create short.

24
MOSIS SCMOS design rules

• Designed to scale across a wide range of
  technologies.
• Designed to support multiple vendors.
• Designed for educational use.
• Ergo, fairly conservative.

25
? and design rules

• ? is the size of a minimum feature.
• Specifying ? particularizes the scalable rules.
• Parasitics are generally not specified in ??units?

26
Wires
metal 3
6
metal 2
3
metal 1
3
pdiff/ndiff
3
poly
2
27
Transistors
2
2
3
3
1
5
28
Vias

• Types of via metal1/diff, metal1/poly,
  metal1/metal2.

4
4
1
2
29
Metal 3 via

• Type metal3/metal2.
• Rules
• cut 3 x 3
• overlap by metal2 1
• minimum spacing 3
• minimum spacing to via1 2

30
Tub tie
4
1
31
Spacings

• Diffusion/diffusion 3
• Poly/poly 2
• Poly/diffusion 1
• Via/via 2
• Metal1/metal1 3
• Metal2/metal2 4
• Metal3/metal3 4

32
Overglass

• Cut in passivation layer.
• Minimum bonding pad 100 ?m.
• Pad overlap of glass opening 6
• Minimum pad spacing to unrelated metal2/3 30
• Minimum pad spacing to unrelated metal1, poly,
  active 15

33
Example 1
34
Color codes

• PolySilicon -- Red
• Ndiffusion -- Green
• Pdiffusion -- Brown
• Metal1 -- Blue
• Metal2 -- Purple
• Contacts/Via -- Black X
• Nsubstrate Contact -- Green X
• Psubstrate Contact -- Brown X

35
Stick diagrams

• A stick diagram is a cartoon of a layout.
• Does show all components/vias (except possibly
  tub ties), relative placement.
• Does not show exact placement, transistor sizes,
  wire lengths, wire widths, tub boundaries.

36
Stick layers
metal 3
metal 2
metal 1
poly
ndiff
pdiff
37
Dynamic latch stick diagram
VDD
in
out
VSS
phi
phi
38
Sticks design of multiplexer

• Start with NAND gate

39
NAND sticks
VDD
a
out
b
VSS
40
One-bit mux sticks
VDD
N1 (NAND)
N1 (NAND)
N1 (NAND)
ai
a
a
bi
a
out
out
out
select
select
b
b
b
VSS
41
3-bit mux sticks
select
select
m2(one-bit-mux)
select
select
VDD
ai
oi
a2
o2
VSS
bi
b2
m2(one-bit-mux)
select
select
VDD
ai
a1
oi
o1
VSS
bi
b1
m2(one-bit-mux)
select
select
VDD
ai
a0
oi
o0
VSS
bi
b0
42
Layout design and analysis tools

• Layout editors are interactive tools.
• Design rule checkers are generally
  batch---identify DRC errors on the layout.
• Circuit extractors extract the netlist from the
  layout.
• Connectivity verification systems (CVS) compare
  extracted and original netlists.

43
Automatic layout

• Cell generators (macrocell generators) create
  optimized layouts for ALUs, etc.
• Standard cell/sea-of-gates layout creates layout
  from predesigned cells custom routing.
• Sea-of-gates allows routing over the cell.

44
Standard cell layout
routing area
routing area
routing area
routing area
45

• Lecture 12
• Cadence Tutorial
• Jan. 31, 2003

46
Cadence Tutorial

• Lab 1

47
Assignment 1

• Questions 2.1, 2.2, 2.5, 2.6, 2.7, 2.9
• Due date Feb. 12, 2003 1200 pm
• Drop off EC 2135

48

• Lecture 13
• Chapter 2 Review
• Feb. 3, 2003

49
Review of Chapter 2

• Digital characteristics of transistor
• Current characteristics of transistor
• Capacitance of transistor
• Wire and via
• Design rules and stick diagram

50
Contents of the Course

• ASIC FPGA
• Transistor and Layout
• Gate and Schematic
• Systems and VHDL/Verilog

51
Examples

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