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Progettazione di circuiti e sistemi VLSI
Anno Accademico 2008-2009 Lezione 7 Circuiti
sequenziali
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Naming Conventions

• In our text
• a latch is level sensitive
• a register is edge-triggered
• There are many different naming conventions
• For instance, many books call edge-triggered
  elements flip-flops
• This leads to confusion however

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Latch versus Register

• Latch
• stores data when clock is low

• Register
• stores data when clock rises

D
Q
D
Q
Clk
Clk
Clk
Clk
D
D
Q
Q
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Maximum Clock Frequency
Also tcdreg tcdlogic gt thold tcd
contamination delay minimum delay
tclk-Q tp,comb tsetup T
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Mux-Based Latches
Negative latch (transparent when CLK 0)
Positive latch (transparent when CLK 1)
CLK
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Master-Slave (Edge-Triggered) Register
Two opposite latches trigger on edge Master
negative latch/ Slave positive latch Also called
master-slave latch pair
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Master-Slave Register
Multiplexer-based latch pair
Positive edge triggered
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Avoiding Clock Overlap
X
CLK
CLK
Q
A
D
B
CLK
CLK
(a) Schematic diagram
CLK
CLK
(b) Overlapping clock pairs
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Other Latches/Registers C2MOS
Keepers can be added to make circuit
pseudo-static
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Non-Bistable Sequential Circuits-Schmitt Trigger

• VTC with hysteresis
• Restores signal slopes

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Noise Suppression using Schmitt Trigger
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Transition-Triggered Monostable
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