ABC Asynchronous Bit-stream Compression

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ABC Asynchronous Bit-stream Compression
MATRICS Research Group
Technion Israel Institute of Technology

• Arkadiy Morgenshtein, Avinoam Kolodny, Ran Ginosar

MATRICS Research Group, Electrical Engineering
Department Technion Israel Institute of
Technology Haifa, Israel
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Background Motivation
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Synchronous Serial Link
? Fast Clock generation is problematic ?
Sensitive to timing uncertainty on chip
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Asynchronous Serial Link

• Fast operation
• No need for clock
• ? Insensitive to timing uncertainty

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Motivation
Limited Bandwidth
Bit-stream Compression
Asynchronous
(ABC)
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ABC Concept
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Asynchronous Signaling
Data
0
1
0
1
1
0
0
1
0
1
1
1

• Level Encoded Dual Rail
• Each bit on two wires
• One wire (S) is the state (0, 1)
• The other wire (P) helps with phase
• To change from one value to the next
• If different value, toggle S
• If same value, toggle P
• Only one wire toggles
• No need for Clock!

S
0
1
0
1
1
0
0
1
0
1
1
1
LEDR
P
0
0
0
0
1
0
1
0
0
0
1
0
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ABC Concept
Data
0
1
0
1
1
0
0
1
0
1
1
1

• Level Encoded Dual Rail
• Each bit on two wires
• One wire (S) is the state (0, 1)
• The other wire (P) helps with phase
• To change from one value to the next
• If different value, toggle S
• If same value, toggle P
• Only one wire toggles
• No need for Clock!

What if both signals would toggle?
S
0
1
0
1
1
0
0
1
0
1
1
1
LEDR
P
0
0
0
0
1
0
1
0
0
0
1
0
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ABC Concept
The new transitions can be used for

• Asynchronous Bit-stream Compression
• Identify a sequence of identical bits
• Mark the beginning of the sequence by one of the
  ABC transitions
• Transmit the length of the sequence
• Mark the end of the encoding by one of the ABC
  transitions.

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Example of ABC Savings
sequence
Data
0
1
0
1
1
0
0
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
0
S
0
1
0
1
1
0
0
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
0
LEDR
P
0
0
0
0
1
0
1
0
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
0
1
1
Transmission starts in regular LEDR mode
Beginning of compression is marked by ABC
transition
The length of the sequence is encoded and
transmitted
The end of the compression is marked by ABC
transition
Transmission continues in regular LEDR mode
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ABC Architecture
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ABC Transmitter
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ABC Transmitter

• Sequence Detectors
• Scan Windows
• Eight 2-bit XORs
• XORs compare sequent bits
• Sequence Detectors
• Identify sequences
• Store the indices and lengths in sequence
  registers

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ABC Transmitter

• Controller
• Sequence Stapler
• Combines sequences
• Produce final indices
• Controller
• Signals when compression starts and ends
• Transmits the sequence length
• Moves the pointer of MUX to next bit after the
  sequence

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ABC Transmitter

• ABC State Machine
• LEDR mode
• Standard protocol
• One signal toggles each time
• ABC mode
• Compression performed
• ABC activated by Controller
• ABC transitions symbolize the start and the end
  of compression

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ABC Receiver
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ABC Receiver

• Clock Generator
• Translates the transitions in S and P signals
  into clock pulses.
• Synchronizes the data storage in the register,
  controls the FSM.
• Identify the ABC transitions used for
  compression beginning.
• Toggles the input to FSM when ABC starts,
  switching to a different operation mode.

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ABC Receiver

• Enabling Decoder
• Converts the data from serial to parallel.
• Provides enable signals to all cells for data
  storage
• In LEDR only one cell is enabled in every cycle
  
• In ABC multiple cells are enabled according to
  from and till indices.
• All the cells in ABC get the same value in one
  cycle - fast storage

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ABC Receiver
Receiver FSM

• Count mode
• With each clock an internal counter is increased
  by one.
• The counter controls the enabling decoder.

• Comp_Decode mode
• Activated when ABC identified
• Stable while the sequence length code is received

• Comp_Decode mode
• Activated when the length is received
• Creates the from and till signals for Enabling
  Decoder
• Returns to Count at next clock

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Design Considerations
Trade-offs
Alternative
Maximal throughput - Increased area and power Add a register to contain two packets. Detect sequences in one packet while transmitting the other packet.
No additional register is needed - Increased transmission time Delaying the transmission by 8 clocks. Allow the scanning of all the bits and detection of the sequences.
Reduced latency, area and power - Reduced ABC compression efficiency Transmit the first 8 bits without ABC. Scan and detect sequences in the remaining 24 bits.
our architecture
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Results
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ABC in Random Packets

• ABC system - transmitter, receiver and 32-bit
  registers - was designed using VHDL
• Transmission time evaluation of the uncompressed
  packet was 655ns
• For maximal compression rate, the transmission
  time was reduced by 55 to 295ns

Simulation of ABC with a series of 100 random
packets with various number and lengths of
sequences
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Image Transmission by ABC
Images with various differentiation were used for
ABC effectiveness evaluation

(c) (b) (a) Image
6.5 10 25 Image size kb
0.13 0.20 0.51 TX original ms
0.06 0.13 0.47 TX by ABC ms
54 36 9 TX reduction
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Summary

• Asynchronous Bit-stream Compression proposed
• ABC targets improvement of BW utilization
• Significant saving in transmission time and power
  
• ABC interfaces were implemented and simulated
• Number of transitions was reduced by up to 54

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Questions?