Application of Binary Translation to Java Reconfigurable Architectures

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Application of Binary Translation to Java
Reconfigurable Architectures

• Antonio Carlos S. Beck Filho
• caco_at_inf.ufrgs.br
• Luigi Carro
• carro_at_inf.ufrgs.br
• Instituto de Informática - GME
• Universidade Federal do Rio Grande do Sul

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Introduction
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• The embedded system market is expanding

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Introduction
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• The embedded system market is expanding

More performance is required
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Introduction
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• Moreover
• Shorter Design cycle
• The complexity of these embedded systems is
  increasing as well
• Battery dependent

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Introduction
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• These embedded systems are adopting Java
• Devices with Java as cellular phones and PDAs
• 176 million in 2001
• 721 million in 2006 1
• 80 of cellular phones will support Java 2
• 10 times more embedded system developers than
  general-purpose software ones by the year 2010 3

1 D. Takahashi, Java Chips Make a Comeback, Red
Herring, 2001 2 G. Lawton, Moving Java into
Mobile Phones, Computer, vol. 35, n. 6, 2002,
pp. 17-20 3 R.W. Atherton, Moving Java to the
Factory. IEEE Spectrum, 1998, pp. 18-23,
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Introduction
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• The Java Language...

• Object Oriented
• Modeling
• Programation
• Validation
• Widely spread
• Safe
• Small size of ROM memory (CISC)
• Multiplataform

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Motivation
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• How to increase the performance with
• low power consumption?

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Motivation
2

• How to increase the performance with
• low power consumption?
• Using a reconfigurable array!

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Motivation
2

• How to increase the performance with
• low power consumption?
• Using a reconfigurable array!

Special tools and compilers are needed!
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Motivation
2

• How to increase the performance with
• low power consumption?
• Using a reconfigurable array!

Special tools and compilers are needed!
No software portability!
And the design cycle?
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Motivation
2

• How to increase the performance with
• low power consumption?
• Using a reconfigurable array!

Special tools and compilers are needed!
No software portability!
And the design cycle?
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Outline
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• Java processors
• Using Binary Translation with reconfigurable
  arrays
• The reconfigurable array
• Results
• Area
• Performance
• Power consumption
• Conclusions and Future Work

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Femtojava Low-Power
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Femtojava Low-Power
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• Five stages

Instruction Fetch
Operand Fetch
Decoder
Execution
Write Back
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Femtojava Low-Power
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IADD
Instruction Fetch
Operand Fetch
Decoder
Execution
Write Back

• With a instruction queue of 9 bytes long to
  handle with variable size instructions

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Femtojava Low-Power
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IADD
11011
Instruction Fetch
Operand Fetch
Decoder
Execution
Write Back

• Responsible for the generation of the microOPs
  and for checking data dependence

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Femtojava Low-Power
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4
POP
Top of Stack
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2
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8
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Instruction Fetch
Operand Fetch
Decoder
Execution
Write Back

• It has a register bank with two ports
• Stack and local variable storage implemented in
  this register file

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Femtojava Low-Power
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4
POP
Top of Stack
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2
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8
3
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Instruction Fetch
Operand Fetch
Decoder
Execution
Write Back

• It has a register bank with two ports
• Stack and local variable storage implemented in
  this register file

Allows comparisons with RISC machines!
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Femtojava Low-Power
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4

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Instruction Fetch
Operand Fetch
Write Back
Decoder
Execution

• Six functional units multiplier, ALU, shifter,
  constant generator, branch and LD/ST

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Femtojava Low-Power
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Top of Stack
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8
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Instruction Fetch
Operand Fetch
Decoder
Execution
Write Back

• Write the results back to the stack or local
  variable storage

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VLIW Architecture
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• 2 instructions/VLIW packet

Instruction 2
Instruction 1
Instruction Fetch
Operand Fetch
Decoder
Execution
Write Back

• VLIW packet has a variable size
• In this case, The VLIW packet can have 1 or 2
  instructions/packet

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VLIW Architecture
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Instruction 1
11011
Decoder 1
Instruction Fetch
Operand Fetch
Write Back
Execution
Decoder 2
Instruction 2
11011

• Decoder 2 doesnt support calls and return of
  methods

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VLIW Architecture
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Register Bank 2
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OperandStack
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Register Bank 1
OperandStack
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Local Variable Pool
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Instruction Fetch
Operand Fetch
Decoder
Execution
Write Back

• Each flow has its own operand stack
• The local variable pool of the method is shared

No mechanism is necessary for communication among
the flows!
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VLIW Architecture
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Instruction Fetch
Operand Fetch
Write Back
Decoder
Execution

• Six functional units multiplier, ALU, shifter,
  constant generator, branch and LD/ST
• They are replicated in each flow

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VLIW Architecture
5
Instruction Fetch
Operand Fetch
Decoder
Execution
Write Back

• Write the results back to the operand stack of
  each flow OR to local variable storage of the 1st
  register bank

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Why use a reconfigurable array?

• Hypothesis substitution of a sequence of
  instructions by a combinational circuit saves
  power (we loose area)
• Let us see the multiplication algorithm example
• TCalg n(TPFFnT?Tset)
• TCCC n nT? (very pessimistic)

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The Binary Translation
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• BT take a binary code and produce another binary
  for a different machine
• BT advantages when used with reconfiguration
• One can detect paralelism and reconfigure the
  array at run-time
• No need for special tools or compilers anymore!
• We solve the sw-compatibility problem

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The Binary Translation
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• How it works?
• Observe the bytecodes looking for frequently
  executed sequences
• Save this sequence in a special cache
• When this sequence of instructions is found
  again, the array is reconfigured and set as
  active functional unit

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Bytecodes Detection
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Bipush 10 Bipush 5 Imul Bipush 3 Bipush
4 Ishl Iadd Istore Bipush 6 Bipush 7 imul
Considering these bytecodes
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Bytecodes Detection
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Bipush 10 Bipush 5 Imul Bipush 3 Bipush
4 Ishl Iadd Istore Bipush 6 Bipush 7 imul
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Bytecodes Detection
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Bipush 10 Bipush 5 Imul Bipush 3 Bipush
4 Ishl Iadd Istore Bipush 6 Bipush 7 imul
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Bytecodes Detection
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Bipush 10 Bipush 5 Imul Bipush 3 Bipush
4 Ishl Iadd Istore Bipush 6 Bipush 7 imul
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Bytecodes Detection
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Bipush 10 Bipush 5 Imul Bipush 3 Bipush
4 Ishl Iadd Istore Bipush 6 Bipush 7 imul
The instructions depend on each other!
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Bytecodes Detection
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Bipush 10 Bipush 5 Imul Bipush 3 Bipush
4 Ishl Iadd Istore Bipush 6 Bipush 7 imul
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Bytecodes Detection
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Bipush 10 Bipush 5 Imul Bipush 3 Bipush
4 Ishl Iadd Istore Bipush 6 Bipush 7 imul
These two blocks are independent !!!
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Bytecodes Detection
7
Bipush 10 Bipush 5 Imul Bipush 3 Bipush
4 Ishl Iadd Istore Bipush 6 Bipush 7 imul
Operand Block 1 First Sequence
Operand Block 2 Second Sequence
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The Reconfigurable Array
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• The array is coarse-grain
• It allows to save a great number of sequences in
  the cache
• The reconfiguration is fast

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The Reconfigurable Array
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• The array is coarse-grain
• It allows to save a great number of sequences in
  the cache
• The reconfiguration is fast
• It is formed by one or more basic cells
• With one multiplier and a sequence of seven sets
  of basic functional units

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General Overview
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Reconfiguration Cache
Array
. . .
Detector Unit
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Power Simulator
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• CACO-PS
• Cycle Accurate COnfigurable Power Simulator

• Based on the switching activity
• Pd a . fc . C . Vdd²

• Result is given in number of gate capacitances
  that switch

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Results
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• A set of algorithms were executed in the
  architectures
• Sin Calculation
• Sort Bubble
• Sort Select
• Sort Quick (10 and 100 elements)
• Search Binary
• Search Sequential
• IMDCT (plus three unrolled versions)
• Floating Point Sums emulation
• Full MP3 PLAYER

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Performance
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Performance
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Performance
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The same number of different sequences of
instructions
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Performance
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Parallelism exposed by loop unrolling
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Performance
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Parallelism exposed by loop unrolling
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Performance
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No more parallelism available!
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Performance
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No more parallelism available!
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Performance
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There is room for improvement!
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Performance
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Energy in memory accesses
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Energy in the cores
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Total Energy Consumption
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Area
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VLIW 2
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Final Results
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VLIW 2
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Conclusions
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• With BT, a reconfigurable array and Java we
  achieve at the same time
• The Java concept of write once, run everywhere
• Software portability for different machines
• Performance
• Low Energy Consumption
• thanks to combinational circuits and paralelism
• we still can reduce Vdd
• HW upgrades with SW compatibility

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Future Works (I)
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• Use Binary Translation with CMP
• At run-time detect what is the best core to
  execute the software at certain time

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Future works (II)

• Implement the BT and reconfigurable array in
  traditional RISC machines
• What are the differences of implementation?

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The end...

• Questions?
• carro_at_inf.ufrgs.br
• caco_at_inf.ufrgs.br

?