Behavior Description

1
Behavior Description

• Lecture 10

2
Behavior Code

• It serves as the specification
• It controls the simulation
• It may be synthesizable

3
Module Structure
module my_module() assign //
continuous assignment and () //
instantiation of primitive adder_16 M() //
instantiation of module always _at_()
begin end initial begin end
endmodule
Structural, no order
Behavior, run in order
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Initial Construct

• Run once
• Set initial value, create waveform
• Used only in testbench
• Not synthesizable

initial begin 10 sig_a 0 10
sig_b 1 sig_c 0 end
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Always Construct

• Infinite loop until simulation stops
• Create waveform
• Used in testbench and module
• Some are synthesizable

always 10 clock clock initial begin
clock 0 100 finish end
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Procedural Assignment

• Used in Initial and Always constructs
• Assign values to registers only
• Procedural assignment (blocking)
• Each assignment is completed before the next
  assignment starts
• Procedural assignment (non-blocking)

a 0 a 1 c a // c 1
a 0 a lt 1 c a // c 0
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Blocking and Non-blocking
initial begin a 0 b 1 a
lt b // a1 b lt a // b0 end
initial begin a 0 b 1
a b // a1 b a // b1 end
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Procedural Continuous Assignment (PCA)

• assign deassign
• Assign value to registers
• The binding can not be removed until deassign
• Overwrite procedural assignment to the target
  register

One shot
a b assign a b
Whenever b changes, a changes accordingly
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Example
module Flop_PCA(preset, clear, q, qbar, clock,
data) input preset, clear, clock, data
output q, qbar reg q assign qbar q
always _at_(nededge clock) q data always
_at_(clear or preset) begin if (!clear)
assign q 0 else if (!preset) assign q
1 else deassign q end endmodule
Synchronous
Asynchronous Overwriting!
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Example 7.4
module mux4_PCA(a, b, c, d, select, y_out)
input a, b, c, d input 10 select output
y_out, reg y_out always _at_(select) begin
if (select 0) assign y_outa else
if (select 1) assign y_outb else if
(select 2) assign y_outc else if
(select 3) assign y_outd else assign
y_out1bx end endmodule
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Alternative
module mux4_PCA(a, b, c, d, select, y_out)
input a, b, c, d input 10 select output
y_out, reg y_out always _at_(select or a or b or
c or d) begin if (select 0)
y_outa else if (select 1) y_outb
else if (select 2) y_outc else if
(select 3) y_outd else y_out1bx
end endmodule
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Procedural Continuous Assignment (PCA)

• force release
• Assign value to nets and registers
• The binding can not be removed until release
• Overwrite primitive, continuous assignment, and
  assign-deassign PCA

Continuous assignment
assign a b force a b
Inside a behavior
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Force and Release

• To have a net or register hold a particular value
  during simulation
• you need to force that to happen
• when you are done, release the effect
• Not synthesizable

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Example (7.6 on page 171)

• Sensitization of a path
• force a1, force b1 release a release b

b
Circuit
a
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Comparison

• Continuous assignment
• assign abc
• Assign values to nets only
• Permanent biding
• Procedural assign
• abc
• Assign values to registers only
• One-time biding
• Inside of Initial and Always construct

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Comparison (contd)

• Procedural Continuous Assignment (PCA)
• assign abc deassign
• Assign values to registers only
• force abc release
• Assign values to nets and registers
• Permanent biding
• Inside of Initial and Always construct
• Overwrite other assignments

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Delay Control

• Operator suspends the activity flow at the
  location of the operator

initial begin clock_period/2 clock
clock end initial 1000 finish
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Event Control

• Operator _at_ synchronizes execution to an event

Activity flow suspended until signal_1 changes
value
_at_signal_1 ab _at_(event_a) begin
_at_(event_b) begin end end
Activity of event_b ignored while waiting
for event_a
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Posedge and Negedge

• posedge 0-gt1, 0-gtx, x-gt1
• negedge 1-gt0, 1-gtx, x-gt0

always _at_(posedge clk) begin _at_(negedge
clk) ab end always _at_(posedge clk) 10
qdata // qdata(clk10) always _at_(negedge
clk) clk clk // not allowed!
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Event Or
Check if anything in the list changes value
always _at_(set or reset or posedge clk) begin
if (reset 0) q 0 else if (set
0) q 1 else if (clk 1) q data
end Is this correct?