EE40 Final Exam Review Prof. Nathan Cheung

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EE40Final Exam ReviewProf. Nathan Cheung

• 12/01/2009

Practice with past exams http//hkn.eecs.berkeley.
edu/exam/list/?exam_courseEE2040
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Overview of Course
Circuit analysis Laws Ohms, KVL, KCL
? Equivalent circuits (series/ parallel,
Thevenin, Norton) ? Superposition for linear
circuits ? Nodal analysis ? Mesh analysis
? Phasor I and V
Circuit components R, C, L , sources
I-V characteristics energy
storage/dissipation
First-order transient excitation/analysis Second
Order RLC circuits Bode Plots
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Overview of Course
Logic gates Combinatorial logic
(sum-of-products, Karnaugh maps), sequential
logic etc.
Semiconductors Devices pn-diodes (many types)
FETs (n-channel, p-channel, CMOS)
Useful Diode and FET circuits Amplifiers
op-amp (negative feedback), rectifiers wave
shaping circuits
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Diode Circuit Analysis by Assumed Diode States

• 1) Specify Ideal Diode Model or Piecewise-Linear
  Diode Model
• 2) Each diode can be ON or OFF
• 3) Circuit containing n diodes will have 2n
  states
• 4) The combination of states that works for ALL
  diodes (consistent with KVL and KCL) will be the
  solution

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Example Problem Perfect Rectifier Model
Suggested problem What if there is a 0.6V drop
when diodes are on ?
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Diode with Capacitor Circuit (e.g.Level Shifter)
VC
VIN(min)
VOUT (t) VC(t) VIN(t)
Finds out what happens to VC when VIN changes
1) Diode open, VC(t)0, VOUT (t) VIN(t) 2)
Diode short, VC(t) -VIN(t) , VOUT(t)0 3) Diode
open, VC(t) -VIN(min), VOUT(t) VIN(t)-VIN(min)
,
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Example Diode with RL Circuit
Sketch i(t)
Answer
Note i(t) is continuous
? L/R 0.05 msec
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Load-Line Analysis
We have a circuit containing a two-terminal
non-linear element NLE, and some linear
components.
First replace the entire linear part of the
circuit by its Thevenin equivalent.
Then define I and V at the NLE terminals
(typically associated signs)
1V
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Example of Load-Line Analysis (cont)
Given the graphical properties of two terminal
non-linear circuit (i.e. the graph of a two
terminal device)
And have this connected to a linear (Thévenin)
circuit
Whose I-V can also be graphed on the same axes
(load line)
Application of KCL, KVL gives circuit solution
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Example Voltage controlled Attenuator
VC and RC Determines rd at Q point of diode
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Example Voltage Controlled Attenuator
The large capacitors and DC bias source are
effective shorts for the ac signal in
small-signal circuits
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Three-Terminal Parametric Graphs
Concept of 3-Terminal Parametric Graphs We
set a voltage (or current) at one set of
terminals (here we will apply a fixed VGS, IG0)
and conceptually draw a box around the device
with only two terminals emerging so we can again
plot the two-terminal characteristic (here ID
versus VDS).
But we can do this for a variety of values of VGS
with the result that we get a family of curves.
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Graphical Solutions for 3-Terminal Devices
We can only find a solution for one input (VGS)
at a time
First select VGS (e.g. 2V) and draw ID vs VDS for
the 3-Terminal device.
Now draw ID vs VDS for the 2V - 200KW Thevenin
source.
The only point on the I vs V plane which obeys
KCL and KVL is ID 5mA at VDS 1V.
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SOLVING MOSFET CIRCUITS STEPS

1. Guess the mode of operation for the transistor.
   (We will learn how to make educated guesses).
2. Write the ID vs. VDS equation for this guess mode
   of operation.
3. Use KVL, KCL, etc. to come up with an equation
   relating ID and VDS based on the surrounding
   linear circuit.
4. Solve these equations for ID and VDS.
5. Check to see if the values for ID and VDS are
   possible for the mode you guessed for the
   transistor. If the values are possible for the
   mode guessed, stop, problem solved. If the values
   are impossible, go back to Step 1.

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CHECKING THE ANSWERS
NMOS

• 1) VGS gt VT(N) in triode or saturation
• VGS VT(N) in cutoff
• 2) VDS lt VGS VT(N) in triode
• VDS VGS VT(N) in saturation

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Example Problem MOSFET Circuit
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Example Problem MOSFET Circuit
Find VGS such that VDS2V
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Example Problem MOSFET Circuit
Find small-signal model parameters
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How do you guess the right mode ?
Often, the key is the value of VGS. (We can
often find VGS directly without solving the whole
circuit.)
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How do you guess the right mode ?
When VGS gtgt VTH(N), its harder to guess the mode.
ID
triode mode
saturation mode
VGS - VTH(N)
If ID is small, probably triode mode
VDS
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EXAMPLE

1. Since VGS gt VTH(N), not in cutoff mode. Guess
   saturation mode.

2) Write transistor ID vs. VDS

• Write ID vs. VDS equation using KVL

GIVEN VTH(N) 1 V, K 250 m A/V2, l 0 V-1.
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EXAMPLE

• Solve VDS
• ID 1mA VDS 2.5 V
• Check
• ID and VDS are correct sign, and VDS VGS-VT(N)
  as required in saturation mode.

GIVEN VTH(N) 1 V, ½ W/L mnCOX 250 m A/V2,
l 0 V-1.
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WHAT IF WE GUESSED THE MODE WRONG?

1. Since VGS gt VTH(N), not in cutoff mode. Guess
   triode mode.

2) Write transistor ID vs. VDS
ID 225010-6(3 1 VDS/2)VDS

• Write ID vs. VDS equation using KVL

GIVEN VTH(N) 1 V, K 250 m A/V2, l 0 V-1.
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WHAT IF WE GUESSED THE MODE WRONG?

• Solve for VDS with quadratic
• equation by combining 2) and 3)
• VDS 4 V, 2.67 V
• 5) Check
• VDS gt VGS VT(N) 2V
• Neither value valid in triode mode!
• Guess is incorrect.

GIVEN VTH(N) 1 V, K 250 m A/V2, l 0 V-1.
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Another Perspective
This circuit acts like a constant current source,
as long as the transistor remains in saturation
mode. IDSAT does not depend on the attached
resistance if saturation is maintained.
In this circuit, the transistor delivered a
constant current IDSAT to the 1.5 kW resistor.
1.5 kW
D
ID
VDS _
G
4 V
VGS _
1.5 kW
IDSAT
3 V
S
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Another Perspective

• The circuit will go out of saturation mode if
• VGS lt VT(N) or
• VDS lt VGS VT(N)
• This can happen if VGS is too large or too small,
  or if the load resistance is too large.

IDSAT does depend on VGS one can adjust the
current supplied by adjusting VGS.
RL
D
ID
VDS _
G
VDD
VGS _
RL
IDSAT
VGS
S
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ANOTHER EXAMPLE

• What is VGS?
• No current goes into/out gate.
• VGS 3 V by voltage division.
• Guess saturation (randomly).

1.5 kW
2 kW
D
ID
G
4 V
2) Write transistor ID vs. VDS
VDS _
VGS _
6 kW

• Write ID vs. VDS equation using KVL

S
GIVEN VTH(N) 1 V, K 250 m A/V2, l 0 V-1.
VDS2.75V consisitent with saturation mode
Effectively the same circuit as previous example
only 1 voltage source in this case
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The CMOS Inverter Current Flow
N sat P sat
VOUT
N off P Triode
C
V
DD
VDD
S
G
N sat P Triode
D
VOUT
VIN
B
D
E
A
D
N Triode P sat
G
S
N Triode P off
0
VIN
VDD
0
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Another CMOS Example The LATCH
VDD
VDD
Data (VIN) is written to the internal node
(VOUT_INT) when the clock is low. VOUT remains
frozen. When the clock is high. The (inverted)
internal node voltage is written to VOUT. The
internal node VOUT_INT remains frozen
CLK
VOUT
VOUT_INT
VIN
CLK
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THE LATCH
When CLK is low the left-hand transistors
conduct. The right-hand transistors are
open. VOUT_INT is charged to VIN.
VDD
VDD
CLK
0 V
VDD
VOUT
VOUT_INT
VIN
VOUT remains the same there is no charging path.
CLK
VDD
0 V
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THE LATCH
When CLK is high, the right-hand transistors
conduct. the left-hand transistors are open.
VDD
VDD
CLK
VDD
0 V
VOUT
VOUT_INT
VIN
CLK
VOUT_INT remains the same there is no charging
path.
VDD
0 V
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CONCEPT OF STATE
VDD
VDD
A latch stores a 1 or 0. The stored value is
known as the state.
CLK
Current State
Next State
This is one of the basic elements needed to make
a state machine (covered in EE 20 and CS 61C).
VIN
CLK
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LATCH AS GATEKEEPER
A signal may have to go through a complex system
of gates, with paths of different delays
possibility of false output!
Sequential Element Prevents changes in output
until signaled
Combinatorial Logic Signal propagates all the way
through Includes our logic gates NAND, NOT, etc.
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Amplifier Efficiency
Source Pi (10-3V)2/105? 10-11 W
Power Supply A
Load
Source
Amplifier
Load P0 (8V)2/8? 8 W
Power Supplies Ps 15W7.5W 22.5 W
Power Supply B
Amplifier Pd 22.5W10-11W-8W 14.5 W
Amplifier Efficiency ? 8/22.5 36
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Differential Signal and Common Mode Signal

• Redefine the inputs in terms of two other
  voltages
• 1. differential mode input vid ? vi1 vi2
• 2. common mode input vicm ? (vi1 vi2)/2
• so that
• vi1 vicm (vid/2) and vi2 vicm - (vid/2)

common mode gain
differential mode gain
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Common Mode Rejection Ratio

• Example
• Differential signal from sensor 1mV (peak).
• We want outputs signal gt 1V implies Adgt 1000
• Common mode signal 100V (from power line).
• We want common mode signal lt 0.1V implies
• Acm lt10-4
• Therefore CMRR needs to be gt 20log(107) 140dB

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Offset Voltage, Offset Current, and Bias Current
Given Voff2mV IB 100nA Ioff 20nA Acm1 Ad100 B
oth input terminals to ground through 100k?
resistors
Use superposition
Vo Ad(VvoffVIoff) Acmvicm 100(0.0016670.0016
67)1(0.01)0.3343V