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SystemVerilog Basic Committee

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Review of 01/20/03 tele-call minutes Johny will champion this topic ... In phone: Dan Jacobi. Steven Sharp. January 22, 2003. www.accellera.org. 5 ... – PowerPoint PPT presentation

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Title: SystemVerilog Basic Committee


1
SystemVerilog Basic Committee
Johny Srouji (Chair) Karen Pieper (Co-Chair)
2
SV-BC F2F Agenda
  • 0900 0930 Introduction, Charter Reminder,
    Processes
  • Review of 01/20/03 tele-call minutes Johny
    will champion this topic
  • 0930 1020 Issues that will not be addressed
    as part of 3.1 -
  • Prioritize a list of issues that must be
    resolved
  • before mid February 
  • Karen will champion this topic
  • 1020 1030 BREAK
  • 1030 1200 SV-BC 18i, 18h, 18g
  • Dave Rich Cliff Cummings will champion this
    slot
  • 1200 - 1230 Lunch
  • Everyone will champion this one ?

3
SV-BC F2F Agenda
  • 1230 - 1400 Discuss/Finalize Peter open
    action items list
  • Peter Flake will Champion this topic
  •  
  • 1400 1415 BREAK
  • 1415 1445 Discuss Issue 19-67
  • Matt Maidment will champion this topic
  •  
  • 1445 1600 Discuss Issues that have proposals
    ready
  • (see status columns in the issues list)
  •  

4
Expected Attendees List
  • In Person
  • Dennis Brophy
  • Kevin Cameron
  • Cliff Cummings
  • Peter Flake
  • Jay Lawrence
  • Matt Maidment
  • Francoise Martinole
  • Mehdi Mohtashemi
  • Karen Pieper
  • Brad Pierce
  • Dave Rich
  • David Smith
  • Johny Srouji
  • Gord Vreugdenhil
  • In phone
  • Dan Jacobi
  • Steven Sharp

5
SV-BC F2F
  • Charter
  • To address issues exposed in SystemVerilog 3.0
    standard through implementation
  • Cannot re-define SystemVerilog 3.0. SystemVerilog
    3.0 is an Accellera Approved Standard
  • The goal is to make sure we have
  • Clear syntax.
  • Clear semantics.
  • Limited modification based on implementation.

6
SV-BC F2F
  • On the extreme case
  • If there is something which will truly disable
    the language or its usage, this should be
    considered carefully
  • Allow appropriate discussion and debate with the
    different experts and language architects
  • Other SV committees are basing their efforts on
    existing SystemVerilog 3.0
  • We cannot remove or add things unless they are
    based on clear implementation issues

7
SV-BC F2F
  • Processes
  • Proper time is allocated for each topic, to
    permit enough constructive discussion
  • Once time is up, we will follow the voting
    process after a discussion of each of the issues
  • Voting rights
  • Everyone can express his/her opinion
  • Those who attended 3 of the last 4 meetings can
    vote
  • Minutes will be summarized and publicized by
    Johny Karen
  • Proposed Email voting process is summarized in
    the next foil

8
Email Voting Process
  • Chair/Co-Chair is eligible to propose a topic for
    email voting
  • Based on the topic complexity
  • Based on whether it has been presented/discussed
    before
  • Motivation resolve simple non controversial
    issues quickly, and better usage of our meetings
    time
  • A committee member can send a note to
    Chair/Co-Chair to propose raising a topic for
    email voting
  • Decision Process
  • A Clear and Documented proposal must be sent
  • A one week time slot will be allocated from
    time of submission
  • Whoever does not vote, will be assumed as not
    objecting
  • If an eligible voting member votes against it,
    the topic must be brought up for a discussion in
    the next meeting
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