Digital Integrated Circuits A Design Perspective

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Digital Integrated CircuitsA Design Perspective
Jan M. Rabaey Anantha Chandrakasan Borivoje
Nikolic
Designing CombinationalLogic Circuits
4/8/04
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Dynamic Logic
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Dynamic CMOS

• In static circuits at every point in time (except
  when switching) the output is connected to either
  GND or VDD via a low resistance path.
• fan-in of n requires 2n (n N-type n P-type)
  devices
• Dynamic circuits rely on the temporary storage of
  signal values on the capacitance of high
  impedance nodes.
• requires on n 2 (n1 N-type 1 P-type)
  transistors

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Dynamic Gate
Mp
Clk
Out
In1
In2
PDN
In3
Me
Clk
Two phase operation Precharge (CLK 0)
Evaluate (CLK 1)
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Dynamic Gate
off
Mp
Clk
on
1
Out
In1
In2
PDN
In3
Me
Clk
off
on
Two phase operation Precharge (Clk 0)
Evaluate (Clk 1)
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Conditions on Output

• Once the output of a dynamic gate is discharged,
  it cannot be charged again until the next
  precharge operation.
• Inputs to the gate can make at most one
  transition during evaluation.
• Output can be in the high impedance state during
  and after evaluation (PDN off), state is stored
  on CL

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Properties of Dynamic Gates

• Logic function is implemented by the PDN only
• number of transistors is N 2 (versus 2N for
  static complementary CMOS)
• Full swing outputs (VOL GND and VOH VDD)
• Non-ratioed - sizing of the devices does not
  affect the logic levels
• Faster switching speeds
• reduced load capacitance due to lower input
  capacitance (Cin)
• reduced load capacitance due to smaller output
  loading (Cout)
• no Isc, so all the current provided by PDN goes
  into discharging CL

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Properties of Dynamic Gates

• Overall power dissipation usually higher than
  static CMOS
• no static current path ever exists between VDD
  and GND (including Psc)
• no glitching
• higher transition probabilities
• extra load on Clk
• PDN starts to work as soon as the input signals
  exceed VTn, so VM, VIH and VIL equal to VTn
• low noise margin (NML)
• Needs a precharge/evaluate clock

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Issues in Dynamic Design 1 Charge Leakage
CLK
Clk
Mp
Out
A
Evaluate
VOut
Clk
Me
Precharge
Leakage sources
Dominant component is subthreshold current
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Solution to Charge Leakage
Keeper
Clk
Mp
Mkp
A
Out
B
Clk
Me
Same approach as level restorer for
pass-transistor logic
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Issues in Dynamic Design 2 Charge Sharing
Charge stored originally on CL is redistributed
(shared) over CL and CA leading to reduced
robustness
Clk
Mp
Out
A
B0
Clk
Me
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Charge Sharing Example
Clk
Out
A
A
B
B
B
!B
C
C
Clk
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Charge Sharing
V
DD
M
Clk
p
Out
C
L
A
M
a
X
C
a

M
B
0
b
C
b
M
Clk
e
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Solution to Charge Redistribution
Clk
Clk
Mp
Mkp
Out
A
B
Clk
Me
Precharge internal nodes using a clock-driven
transistor (at the cost of increased area and
power)
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Issues in Dynamic Design 3 Backgate Coupling
Clk
Mp
Out1
1
Out2
0
In
A0
B0
Clk
Me
Dynamic NAND
Static NAND
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Backgate Coupling Effect
Out1
Voltage
Clk
Out2
In
Time, ns
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Issues in Dynamic Design 4 Clock Feedthrough
Coupling between Out and Clk input of the
precharge device due to the gate to drain
capacitance. So voltage of Out can rise above
VDD. The fast rising (and falling edges) of the
clock couple to Out.
Clk
Mp
Out
A
B
Clk
Me
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Clock Feedthrough
Clock feedthrough
Clk
Out
In1
In2
In3
In Clk
Voltage
In4
Out
Clk
Time, ns
Clock feedthrough
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Other Effects

• Capacitive coupling
• Substrate coupling
• Minority charge injection
• Supply noise (ground bounce)

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Cascading Dynamic Gates
V
Clk
Clk
Mp
Mp
Out2
Out1
In
Clk
Clk
Me
Me
t
Only 0 ? 1 transitions allowed at inputs!
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Domino Logic
Mp
Clk
Mkp
Mp
Clk
Out1
Out2
1 ? 1 1 ? 0
0 ? 0 0 ? 1
In1
In4
PDN
In2
PDN
In5
In3
Me
Clk
Me
Clk
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Why Domino?
Clk
Clk
Like falling dominos!
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Properties of Domino Logic

• Only non-inverting logic can be implemented
• Very high speed
• static inverter can be skewed, only L-H
  transition
• Input capacitance reduced smaller logical
  effort

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Designing with Domino Logic
V
V
DD
DD
V
DD
Clk
M
Clk
M
p
p
M
r
Out1
Out2
In
1
PDN
In
PDN
In
2
4
In
3
Can be eliminated!
M
Clk
M
Clk
e
e
Inputs 0 during precharge
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Footless Domino
The first gate in the chain needs a foot
switchPrecharge is rippling short-circuit
current A solution is to delay the clock for each
stage
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Differential (Dual Rail) Domino
off
on
Clk
Mp
Clk
Mkp
Mkp
Mp
Out AB
Out AB
1 0
1 0
A
!A
!B
B
Me
Clk
Solves the problem of non-inverting logic
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np-CMOS
Me
Clk
Mp
Clk
Out1
1 ? 1 1 ? 0
In4
PUN
In1
In5
In2
PDN
0 ? 0 0 ? 1
In3
Out2 (to PDN)
Mp
Clk
Me
Clk
Only 0 ? 1 transitions allowed at inputs of PDN
Only 1 ? 0 transitions allowed at inputs of PUN
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NORA Logic
Me
Clk
Mp
Clk
Out1
1 ? 1 1 ? 0
In4
PUN
In1
In5
In2
PDN
0 ? 0 0 ? 1
In3
Out2 (to PDN)
Mp
Clk
Me
Clk
to other PDNs
to other PUNs
WARNING Very sensitive to noise!