VHDL Stopwatch with Split

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VHDL Stopwatch with Split

• A presentation
• by Scott Conaton
• and Colin Dolcetti

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Project Objectives

• Build and implement a fully functional stopwatch
  using VHDL programming techniques developed in
  class.
• Demonstrate the use of the stopwatch to the class
  as a whole.

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Design

• We developed several new modules to utilize in
  the main program
• Time_Gen a time value generator, which outputs
  the time elapsed since the input, clkin has been
  set to 1.
• BTNx toggles the value of its output whenever it
  recieves a clock pulse.

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Time_gen

• This module consists of four modified counters,
  tenscnt, onescnt, tenthcnt, and hunscnt.
• The output of each of these counters is its
  corresponding time digit.
• The counters each receive the clock pulse and
  delay it the appropriate time

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Main Program

• The main program takes the time value output by
  time_gen and sends it to the data registers T and
  N.
• The display register, DI, loads the value in N
  into the display module, which then outputs the
  time value to the 7-segment displays

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Main Program Controls

• When either button is pressed, its value is sent
  through a debounce to reduce it to a short clock
  pulse.
• The pulse then travels through the BTNx module
  which, if BTN(1) is pressed, toggles the clkin
  signal, and if BTN(2) is pressed, toggles the
  diload signal.

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Effect of clkin and diload

• Clkin and diload are initially set to 0 and 1
  which stops time_gen, and allows the value in N
  to be loaded into DI and displayed.
• When clkin goes to 1, time_gen begins to count
  and the current value is output to the displays.
• When diload goes to 0, DI no longer loads any new
  values from N.

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Effects (Cont.)

• At this point N still updates from time_gen every
  pulse, but only the last value in DI is
  displayed, until BTN(2) is pressed again,
  resetting diload to 1.
• This is how we created the split effect.

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Demonstration of Stopwatch

• We will now demonstrated the final implementation
  of our stopwatch program
• Please hold your questions until the demo has
  finished.