Synthesizing InterconnectEfficient Low Density Parity Check Codes

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Synthesizing Interconnect-Efficient Low Density
Parity Check Codes

• Marghoob Mohiyuddin Amit Prakash Adnan Aziz
• The University of Texas at Austin
• Wayne Wolf
• Princeton University

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Introduction

• Error correcting codes widely used in
  communication and storage systems
• Shannons work defined tight bounds on error
  correcting capability
• Channel model
• Binary transmission A, -A
• Noise is additive white gaussian
• Two classes of codes come close to
  achievingbounds
• Turbo codes BGT-ICC93
• Low Density Parity Check codes (LDPCs) G62,
  LMSS-TIT01

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Turbo Codes vs. LDPC Codes

• Turbo codes empirical
• LDPCs have some analytical basis
• LDPCs more parallelizable
• Performance and power benefits
• High throughput LDPC implemented at
  LucentBH-JSSC02
• LDPCs selected for next generation digital
  satellite TV (DVB-S2, Nov 2003)

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Low Density Parity Check Codes

• Generalization of using parity bit in error
  detection
• Code bits original message bits check bits
• Check bit parity of subset of message bits
• A codeword satisfies parity check equations
• Represent code by a bipartite graph Tanner
  Graph (code bits vs. parity check equations)
• Girth of graph length of smallest cycle
• Large girth ? better performance CMR-ICC01
• Linear-time decoding algorithms for LDPCs G62
• Our paper is about constructing good codes

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An example
Tanner Graph
Legal Codewords 0 0 0 0 0 0 0 1 1 1 1 0 0 0 1 1
1 0 1 0 1 0 0 0 1 1 0 1
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The Decoding Algorithm G62

• Soft inputs
• Local information (message) exchanged along the
  edges of the Tanner graph
• Decoding logically operates on the Tanner graph
• Message estimate of received bit reliability
  measure of the estimate
• In each iteration
• Code nodes transmit estimate of the receivedbit
  and the reliability measure
• Check nodes then send back new estimates and
  reliabilities based on the messages received

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Hardware Implementation

• Message passing decoder ? fully parallel
  implementation BH-JSSC02
• Implement each node as a functional unit
• Implement edges between the nodes as interconnect
• Each node computes in parallel
• Fact Good LDPC graphs have irregular structure
  LMSS-TIT01
• Implies high routing congestion, leading to large
  number of long wires and larger area
• Our research Generate LDPCs with low congestion,
  and good error correcting capability

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Hardware Implementation BH-JSSC02

• High throughput 1 Gbps
• Utilization 50
• Area determined by routing congestion
• Many long nets
• Most power due to wires
• 0.16u, 1.5 V CMOS, 5 metal layers
• Area 7.5mm X 7mm
• Power 690 mW

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Intuition

• Start by looking at the simplest translation of
  LDPC graph into hardware
• Place code nodes in first row, check nodes in
  second row
• Width of layout fixed
• Height is determined by the edges
• Think of it as a channel with terminals ontop
  and bottom
• Idea Generate LDPC graphs given constraint on
  the channel height with good error correcting
  capability

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Intuition

• Assumed two layers of metal for routing signals
• One for vertical and one for horizontal
• Idea Look at the number of horizontal tracks
  along a column of the layout. This defines a cut
• Lemma Height of the channel maximum numberof
  horizontal tracks in any cut
• All vertical edges crossing a column, need to be
  routed on different horizontal tracks (in that
  column)

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Example Layout
Code Bits
Parity Bits
Layout
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LDPC Generation Algorithm

• Constraints
• Number of code bits c
• Number of parity checks p
• Average degree of check nodes d
• Girth constraint g
• Maximum height of the layout h
• Generate an LDPC graph with the above constraints
• Important to treat nodes uniformly, therefore
• Proceed in iterations
• In each iteration, add at most one edge to a
  nodeThis is a 1-1 mapping!
• Height constraint for 1-1 mapping in each
  iteration
• Bit-filling algorithm CMR-ICC01

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Algorithm

• Repeat the following until edges pd
• Select check node C at random from the set of
  unselected check nodes (for this iteration)
• Compute S, the set of feasible neighbor code
  nodesusing the girth the height constraints
• Select a code node from S, at random asa
  neighbor of C
• Update heights for columns affected
• Different heuristics can be used to selectcode
  nodes
• Instead of total height, we use the height ofthe
  channel during an iteration

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Algorithm Example(Iteration 1)
Min Girth 6 Max Height 2
Max height violated
2
2
1
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Algorithm Example(Iteration 2)
Min Girth violated
1
2
1
Max height violated
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Results
1
h 256
0.1
h 64
Block Error Rate
0.01
0.001
0.0001
0
2
3
4
1
0.7 db
SNR (dB)
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Conclusions and Future Work

• Solves the congestion problem by abstractingit
  to a higher level
• Trades off error correcting capability for VLSI
  implementation cost
• Layout potentially eccentric, a recent work
  (under review) proposes
• A multi-rate reconfigurable architecture for
  LDPC decoding
• An algorithm which takes the aspect ratio into
  account