Fast Timing Closure by Interconnect Criticality Driven Delay Relaxation

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Fast Timing Closure by Interconnect Criticality
Driven Delay Relaxation

• Love Singhal and Elaheh Bozorgzadeh
• Center for Embedded Computer Systems,
• University of California, Irvine

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Outline

• Critical Interconnect
• Delay Relaxation
• CER Algorithm
• Experiments
• Conclusion

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Outline

• Critical Interconnect
• Delay Relaxation
• CER Algorithm
• Experiments
• Conclusion

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Critical Interconnect
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Slack on Edges is zero
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Non-critical edges
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Timing Constraint, T 20 cycles
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Critical Interconnect
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Wire Pipelining
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Timing Constraint, T 20 cycles
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Placement and Routing
Registers free congestion

• Second design has
• Less routing overlap and less congestion
• Easier placement and routing and faster timing
  closure.

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Wire Delay

• Wire delay is significant in FPGAs due to routing
  switches and heterogeneous routing architecture
• On average, 50 of clock period is due to routing
  delay.
• A register added on wire (wire pipelining)
  reduces average wire delay to 60.

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Wire Pipelining Related Work

• C. Lin and H. Zhou, ICCAD 2003
• Retiming for Wire pipelining
• On ASIC
• L. P. Carloni and A. L.Sangiovanni-Vincentelli,
  CODESISSS 2003
• Retiming for long wires in GALS
• J. Cong, Y. Fang, and Z. Zhang, DAC 2004
• Wire pipelining during architecture synthesis
• Our work deals with early planning for wire
  pipelining to avoid long wires

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Outline

• Critical Interconnect
• Delay Relaxation
• CER Algorithm
• Experiments
• Conclusion

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Delay Relaxation

• Delay relaxation or budgeting is assigning extra
  delay to nodes or edges under timing constraint
• Maximal delay budgeting no node can get any more
  delay
• Budgeting improves area and complexity of design
  adds simplification

Timing Constraint, T 20 cycles
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Drawbacks of Delay Relaxation

• Every node has atleast one incoming and one
  outgoing critical edge.
• Maximum budgeting can increase critical edges in
  the graph

Timing Constraint, T 20 cycles
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Delay Budgeting Related Work

• Previous work has concentrated on maximizing
  total budget
• Heuristics, ZSA
• R. Nair, et. al. TCAD 1989
• Polynomial time optimal algorithm for maximum
  budgeting
• S. Ghiasi, E. Bozorgzadeh, S. Choudhary, and M.
  Sarrafzadeh, ICCAD 2004.
• No previous work considers effect of critical
  edges

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Outline

• Critical Interconnect
• Delay Relaxation
• CER Algorithm
• Experiments
• Conclusion

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Problem Formulation

• Problem Given an acyclic data flow graph G
  (V,E), find a Maximal Budgeting B on the nodes
  such that number of Critical Edges is Minimized
  (MB-MCE problem)
• Solutions
• Integer Linear Programming Formulation Optimal
  but Inefficient
• Heuristic CER Algorithm

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Problem Input and Output
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CER Algorithm
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Timing Constraint, T 20 cycles
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An Example
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C
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B
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Budget Reassignment
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An Example
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A
C
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B
D
? 2 -1
? 1 0
A Budget Reassignment, ?, increases delay of
parent node by ? and decreases delay of child
node by ?.
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An Example
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A
C
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B
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Lemma Sufficient Condition for critical edge
reduction in this graph is ? 1 gt ? 2
? 1 gt ? 2
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Larger Critical Bipartite Graph
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E
G
A
C
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F
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B
D
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Larger Critical Bipartite Graph
Find maximum candidate critical edges between
clusters
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Cluster Nodes Our Algorithm
Pick the node with minimum degree as seed
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E
G
C
A
A
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F
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B
F
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D
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Next Task ? 1 gt ? 2
Composite Edges
Composite Nodes
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Assign Deltas to Composite Graph
Q
P
R
S
Q
P
R
S
? Q lt ? P
? P gt ? R gt ? S
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Delta Assignment Problem

• Given a directed acyclic graph, assign delta to
  the nodes such that the number of edges with ?1 gt
  ?2 is maximized, where ?1 and ?2 are deltas of
  the two nodes containing composite edge.
• NP Hard Problem
• Solution Reverse Breadth First Search
• Find an output node
• Assign maximum Delta to it.
• Remove it from graph

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Assign Deltas to Composite Graph
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G
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Q
P
R
S

• ? P 1
• Q 0
• R 0
• S -1

Q
P
R
S
? Q lt ? P
? P gt ? R gt ? S
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Assign Deltas to Composite Graph
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G
A
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F
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Q
P
R
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?Q 0
?P1
?R0
?s-1
3 Critical Edges are reduced after delta
assignment
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Reducing critical edges
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Directed Acyclic Graph

• Parents in critical bipartite graphs have same
  arrival time.
• Djikstra Algorithm picking the minimum arrival
  time nodes
• Make a critical bipartite graph of the chosen
  nodes and process it.
• Preserve existing non-critical edges

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Critical Edge Reduction (CER) Algorithm

• Find Critical Bipartite Graphs
• For each critical bipartite graph,
• Create Composite Graphs
• Assign Deltas to reduce critical edges in
  composite graphs
• Update budgets on nodes

Complexity of CER Algorithm O (V E)
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Outline

• Critical Interconnect
• Delay Relaxation
• CER Algorithm
• Experiments
• Conclusion

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Experiments Design Flow
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Benchmarks
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Results Design Flow
No Budgeting
DFG
Pipelining Module
Our Algorithm (CER)
CPLEX ILP Solution
Maximum Budgeting
Resource and Wire Pipelining
DFG to Verilog Generator
Synplicity Synthesis (with retiming)
Xilinx Place And Route (with highest PAR effort)
Critical Edge Minimization Experiment Design Flow
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Critical Edges and Total Budget
AVERAGE NUMBER OF CRITICAL EDGES AND TOTAL DELAY
BUDGET

• Critical Edges reduced by the algorithm are close
  to ILP
• Total Budget loss is also comparable

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Results Design Flow
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Place and Route Runtime

• Designs using CER algorithm achieve timing
  closure faster than all other cases
• No delay relaxation (No budgeting) leads to more
  congestion

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Clock Period

• The No budgeting technique doesnt give good
  timing with higher PAR time.
• Clock period of ILP and CER algorithm is
  comparable.
• Average clock period of our algorithm is least.
• The clock period is achieved 2.8 times faster
  than maximum budgeting.

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Outline

• Critical Interconnect
• Delay Relaxation
• CER Algorithm
• Experiments
• Conclusion

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Conclusion

• Interconnect criticality can play important role
  in design complexity and final place and route
  stage
• We give a fast, efficient algorithm to reduce
  critical edges in an acyclic dataflow graph
• Compared to existing techniques, our algorithm
  enables incremental delay reassignments.
• For future work, the algorithm can be adapted to
  be more circuit aware.

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Thank You