Timingaware Exceptions for a Precision Timed PRET Target

1
Timing-aware Exceptions for a Precision Timed
(PRET) Target

• Ben Lickly
• Hiren D. Patel
• Edward A. Lee

• Time-based Exceptions
• In some cases it may be necessary to specify what
  happens in case a timing requirement is not met.
  In these cases, we would like to specify
  exception handling code that will handle missed
  deadlines.
• We intend to to use the clang/LLVM compiler
  infrastructure as the base for our exception
  implementation. This is an open-source code base
  written with an emphasis for simplicity and
  extensibility. Relevant features include
• Source code rewriting
• Static analysis
• Code generation for SPARC V8

PRET Philosophy The traditional abstractions used
in computer systems only concern themselves with
the functional aspects of a program. This
allows the use of techniques like speculative
execution, caches, interrupts, and dynamic
compilation that offer improved average-case
performance at the expense of predictable
execution times. The PRET project aims to improve
the timing predictability at all layers of
abstraction by carefully reexamining and
reworking various architectural and compiler
advancements with an eye toward their effects on
timing behavior and worst-case bounds. .

• Programming Models
• One of the models of computation that seems to
  fit very well with the PRET architecture is
  Giotto.
• Advantages
• Time-triggered tasks map very well onto PRET
  hardware threads with timing instructions
• Leverage existing C code generation
  infrastructure of Ptolemy II to automatically
  synthesize PRET programs from Ptolemys Giotto
  models.

clang/LLVM Compilation
Even though the PRET project encompasses all the
abstraction layers of a computer system, this
poster primarily focuses on the middle layers,
such as the instruction-set architecture,
compilers and code generators, and specification
languages. .
Ptolemy II Code Generation
ISA Extensions The instruction-set architecture
is augmented with timing instructions, which
control the execution time of the sequence of
assembly instructions that they surround. There
are variants to specify upper bounds or lower
bounds, but all allow timing control through a
special set of deadline registers.