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Recycler Damper High Frequency Stability

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CIC filter with decimate by 4. Standard approach to bandwidth limit digital receivers ... Decimate by 4 to insure FPGA can keep up. July 6, 2005. Recycler ... – PowerPoint PPT presentation

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Title: Recycler Damper High Frequency Stability


1
Recycler Damper High Frequency Stability
  • Jim Crisp
  • crisp_at_fnal.gov

2
RR Damper Cartoon
3
RR Damper Features
  • Two bpms separated by 90 used to simulate
    optimum betatron phase
  • split tube bpms and 150kohm preamps provide
    flat frequency response from 10KHz to 70MHz
  • Use A-B to avoid problems at low intensity
  • Optimize gain for highest beam intensity
  • One turn delay
  • The error from each pbar is applied to that pbar
  • Digital filter
  • Used to set 1 turn delay and provide comb filter
  • 12 bit 212MHz A/Ds
  • Commercial 100watt solid state amplifiers
  • 10KHz to 230MHz
  • 580nRad max kick (0.58mm max linear betatron
    oscillation)
  • 1.4meter long stripline kicker
  • response is 3db down at 50MHz
  • 50MHz will cover the first 550 rotation harmonics
  • Lowest betatron frequency 35KHz

4
Feedback Loop
  • 1/e time constant 1/open loop gain
  • 100turns for 1urad/mm gain (1 correction/turn)
  • (.5urad/mm should be sufficient V. Balbekov)

5
Stability Requirements
  • GH -1 is a problem
  • The phase shift must be less than 180º when the
    open loop gain is greater than 1
  • Desire 30 to 60º phase margin

6
Damper Components
  • Stability requirement applies to all system
    elements in series
  • BPM
  • Preamp
  • Sum/Difference
  • Anti aliasing filter
  • 70MHz LPF
  • Digital filter
  • Sampling effects
  • CIC/decimation filter
  • Notch filter
  • Amplifier
  • cables
  • Kicker
  • Beam response

7
BPM-Preamp-Sum/Difference
  • 10KHz to 150MHz

8
Anti-aliasing Filter
  • 70MHz LPF
  • (corrected for 15nsec delay)

9
ADC sampling
  • ADC sample rate 4 x 53MHz 212MHz

10
CIC filter with decimate by 4
  • Standard approach to bandwidth limit digital
    receivers
  • Linear phase
  • Decimate by 4 to insure FPGA can keep up

11
Digital notch filter
  • Remove energy at rotation harmonics to limit
    emittance growth
  • Depth of notches about 65db for the 12 bit ADC
  • (If all notches identical, the closed orbit error
    would be reduced by 65db)
  • Noise induced emittance growth 0.5 pi-mm-mRad/Hr
  • 18º phase shift -0.5db at 0.4 and 0.6 times the
    rotation frequency

12
Amplifiers/Cables
  • Amplifier Research KMA2020
  • 100Watt
  • 10KHz to 230MHz
  • Just received Amplifiers Tuesday, will measure
    ASAP
  • BPM cables LDF4-50 (1/2 heliax)
  • 228 to 445 feet
  • 2.34db/100ft_at_1GHz
  • Kicker cables LDF5-50A (7/8 heliax)
  • 117 feet
  • 1.31db/100ft_at_1GHz
  • (Cable delays are used to make up part of the
    required 1 turn delay)

13
Kicker frequency response
  • 1.4 meter long stripline kicker
  • About ½ kick at 65MHz
  • Changes sign at 107MHz
  • Linear phase

14
Overall
  • Need to measure amplifier
  • Some phase error at upper end can be considered
    delay

15
Beam phase response
  • Betatron phase has opposite sign in upper/lower
    sidebands
  • Time delay has same sign

16
Beam Response
  • Corrected for delays and phase advance
  • Betatron phase has opposite phase on upper/lower
    sidebands
  • Delay has same phase for upper/lower sidebands
  • All betatron sidebands will have the same
    gain/phase response shown below
  • As the damper gain increases, instability will
    start at the edges of the distribution
  • Probably at the low or high end of the damper
    frequency range

17
Status 7/6/05
  • Preamps are installed at 2 locations
  • Remaining 2 at next opportunity
  • Power amplifiers arrived yesterday
  • Chassis should be out of the shop this week
  • One digital filter board is stuffed and debugging
    has begun
  • Critical path
  • Would like some proton time to measure/verify
    beam response
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