Virtual Memory

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Virtual Memory
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Outline

• Virtual Space
• Address translation
• Accelerating translation
• with a TLB
• Multilevel page tables
• Different points of view
• Suggested reading 10.110.6

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Physical Addressing

• Attributes of the main memory
• Organized as an array of M contiguous byte-sized
  cells
• Each byte has a unique physical address (PA)
  started from 0
• physical addressing
• A CPU use physical addresses to access memory
• Examples
• Early PCs, DSP, embedded microcontrollers, and
  Cray supercomputers

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Physical Addressing
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Virtual Addressing

• Virtual addressing
• the CPU accesses main memory by a virtual address
  (VA)
• The virtual address is converted to the
  appropriate physical address

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Virtual Addressing

• Address translation
• Converting a virtual address to a physical one
• requires close cooperation between the CPU
  hardware and the operating system
• the memory management unit (MMU)
• Dedicated hardware on the CPU chip to translate
  virtual addresses on the fly
• A look-up table
• Stored in main memory
• Contents are managed by the operating system

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Address Space

• Address Space
• An ordered set of nonnegative integer addresses
• Linear Space
• The integers in the address space are consecutive
• N-bit address space

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Address Space

• K210(Kilo), M220(Mega), G230(Giga),
  T240(Tera), P250(Peta), E260(Exa)

256
255
16
64K-1
4G
4G-1
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256T-1
16E
16E-1
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Address Space

• Data objects and their attributes
• Bytes vs. addresses
• Each data object can have multiple independent
  addresses

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Using Main Memory as a Cache
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Using Main Memory as a Cache

• DRAM vs. disk is more extreme than SRAM vs. DRAM
• Access latencies
• DRAM 10X slower than SRAM
• Disk 100,000X slower than DRAM
• Bottom line
• Design decisions made for DRAM caches driven by
  enormous cost of misses

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Design Considerations

• Line size?
• Large, since disk better at transferring large
  blocks
• Associativity?
• High, to minimize miss rate
• Write through or write back?
• Write back, since cant afford to perform small
  writes to disk

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Page

• Virtual memory
• Organized as an array of contiguous byte-sized
  cells stored on disk conceptually.
• Each byte has a unique virtual address that
  serves as an index into the array
• The contents of the array on disk are cached in
  main memory

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Page

• The data on disk is partitioned into blocks
• Serve as the transfer units between the disk and
  the main memory
• virtual pages (VPs)
• physical pages (PPs)
• Also referred to as page frames

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Page Attributes

• Unallocated
• Pages that have not yet been allocated (or
  created) by the VM system
• Do not have any data associated with them
• Do not occupy any space on disk.

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Page Attributes

• Cached
• Allocated pages that are currently cached in
  physical memory.
• Uncached
• Allocated pages that are not cached in physical
  memory.

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Page
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Page Table

• Each allocate page of virtual memory has entry in
  page table
• Mapping from virtual pages to physical pages
• From uncached form to cached form
• Page table entry even if page not in memory
• Specifies disk address
• OS retrieves information

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Page Table
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Page Table
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Page Hits
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Page Faults

• Page table entry indicates virtual address not in
  memory
• OS exception handler invoked to move data from
  disk into memory
• current process suspends, others can resume
• OS has full control over placement, etc.

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Page Faults

• Swapping or paging
• Swapped out or paged out
• Demand paging

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Servicing a Page Fault
(1) Initiate Block Read

• Processor Signals Controller
• Read block of length P starting at disk address X
  and store starting at memory address Y

Processor
Reg
Cache
Memory-I/O bus
I/O controller
Memory
disk
Disk
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Servicing a Page Fault
Processor

• Read Occurs
• Direct Memory Access (DMA)
• Under control of I/O controller

Reg
Cache
Memory-I/O bus
(2) DMA Transfer
I/O controller
Memory
disk
Disk
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Servicing a Page Fault

• I / O Controller Signals Completion
• Interrupt processor
• OS resumes suspended process

Processor
Reg
(3) Read Done
Cache
Memory-I/O bus
I/O controller
Memory
disk
Disk
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Address Translation

• V 0, 1, . . . , N1 virtual address space
• P 0, 1, . . . , M1 physical address space
• N gt M
• MAP V ? P U ? address mapping function
• MAP(a) a' if data at virtual address a is
• present at physical address a' in P
• ? if data at virtual address a is not
• present in P

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Address Translation
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Address Translation

• Parameters
• P 2p page size (bytes).
• N 2n Virtual address limit
• M 2m Physical address limit

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Address Translation
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Address Translation via Page Table
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Simple Memory System Example

• Addressing
• 14-bit virtual addresses
• 12-bit physical address
• Page size 64 bits

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Simple Memory System Page Table

• Only show first 16 entries

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Address Translation Example
Virtual Address 0x03D4
VPN 0x0f Page Fault? No
PPN 0x0D VPO 0x14 PA 0x354
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Page Hits
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Page Faults
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Integrating Caches and VM
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Integrating Caches and VM

• Most Caches Physically Addressed
• Accessed by physical addresses
• Allows multiple processes to have blocks in cache
  at same time
• Allows multiple processes to share pages
• Cache doesnt need to be concerned with
  protection issues
• Access rights checked as part of address
  translation

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Integrating Caches and VM

• Perform Address Translation Before Cache Lookup
• But this could involve a memory access itself (of
  the PTE)
• Of course, page table entries can also become
  cached

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Speeding up Translation with a TLB

• Translation Lookaside Buffer (TLB)
• Small hardware cache in MMU
• Maps virtual page numbers to physical page
  numbers

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Speeding up Translation with a TLB
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Speeding up Translation with a TLB
n1
0
p1
p
virtual address
virtual page number
page offset
valid
physical page number
tag
.
.
.
TLB

TLB hit
physical address
tag
byte offset
index
valid
tag
data
Cache

data
cache hit
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Simple Memory System TLB

• TLB
• 16 entries
• 4-way associative

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Address Translation Example
Virtual Address 0x03D4
VPN 0x0f TLBI 0x03 TLBT 0x03 TLB Hit? yes
Page Fault? No
PPN 0x0D VPO 0x14 PA 0x354
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Simple Memory System Cache

• Cache
• 16 lines
• 4-byte line size
• Direct mapped

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Simple Memory System Cache
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Address Translation Example
PA 0x354
Offset 0x0 CI 0x05 CT 0x0D Hit? Yes
Byte 0x36
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Multi-Level Page Tables

• Given
• 4KB (212) page size
• 32-bit address space
• 4-byte PTE
• Problem
• Would need a 4 MB page table!
• 220 4 bytes

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Multi-Level Page Tables

• Common solution
• multi-level page tables
• e.g., 2-level table (P6)
• Level 1 table 1024 entries, each of which points
  to a Level 2 page table.
• Level 2 table 1024 entries, each of which
  points to a page

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Representation of Virtual Address Space
Page 15
PT 3
Page 14
Page 13
Page Directory
Page 12
Page 11
PT 2
Page 10
Page 9
Page 8
PT 0
Page 7
Page 6
Page 5
Mem Addr

• Simplified Example
• 16 page virtual address space
• Flags
• P Is entry in physical memory?
• M Has this part of VA space been mapped?

Page 4
Page 3
Disk Addr
Page 2
In Mem
Page 1
On Disk
Page 0
Unmapped
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Multi-Level Page Tables
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Multi-Level Page Tables
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A Tool for Memory Management

• Separate virtual address space
• Each process has its own virtual address space
• Simplify linking, sharing, loading, and memory
  allocation

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A Tool for Memory Management
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A Tool for Memory Management
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A Tool for Memory Protection

• Page table entry contains access rights
  information
• hardware enforces this protection (trap into OS
  if violation occurs)

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A Tool for Memory Protection
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A Tool for Memory Protection