SelfConfigurable Architecture for Reusable Space Systems SCARS

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Self-Configurable Architecture for Reusable Space
Systems (SCARS)

• Team
• Adarsha Sreeramareddy, Chad T. Rossmeissl
• Jeff Josiah, Andrew Lotti (Graduate)
• Jeremy Wright, Kevin Carr (Undergraduate)

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Before SCARS
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FPGA (with memory)
Start
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Isolating Failure
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Project Goals

• Develop a self-healing reconfigurable
  architecture in which individual, modular
  components /subsystems
• respond to hardware/software anomalies
  automatically with self-healing action
• adapt to changes in mission objectives over time
  and optimize computing capability
• coordinate their actions for broader range of
  objectives hence go beyond mission-specific
  requirements
• Objective
• demonstrate advantages and feasibility of such
  architecture based on scenarios that will
  quantify the benefits.

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Capabilities

• Network Level Healing
• Node Level Healing
• Mission Control GUI

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Node Architecture
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Wireless System (I)
Master Node is elected from available Nodes
Each Node within the system shall capture image
and perform a unique function (task) on that
image, then transmit the results to the Master
Node
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Task Distribution (I)
Master Node commands each Node to perform a
specific task and forward its results.
Color Space Transform (CST)
Discrete Wavelet Transform (DWT)
Quantization
FFT
Discrete Cosine Transform (DCT)
Image Scaling
Each Node is capable of performing any of the
functions (tasks)
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Self-Healing , Lost 1 Node (I)
Master Node reassigns task to another Node.
Color Space Transform (CST)
Discrete Wavelet Transform (DWT) Image Scaling
FFT
Discrete Cosine Transform (DCT)
Image Scaling
One node is broken (failed a self-check), not
responding, out of communication range, or out of
power.
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Partial Configuration
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Tools and Mechanisms

• XPS Xilinx Platform Studio
• Builds Microblaze soft processor core
• Instantiates HWICAP
• Defines overall connectivity of the system
• BSB Base System Builder
• Instantiates Microblaze, communication busses
  (Reconfiguration Shared Bus Interface), Partially
  Reconfigurable peripheral modules
• OPB On Chip Peripheral Bus
• Communication between Microblaze and Peripherals
• LMB Local Memory Bus
• Connects instruction and data ports of Microblaze
  to BRAMs

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Node Level Healing (II)
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Tools for Partial Configuration

• HWICAP Core
• Read and write FPGA configuration memory
• Load bitstreams frame by frame through BRAM to
  the ICAP
• PlanAhead
• Import netlists generated by XPS
• ExploreAhead
• Define static module (region)
• Microblaze core, communication busses,
  peripherals
• Bitgen
• Merge partial bitstreams (static and partial
  reconfigurable user logic)
• Routines written in C program Microblaze to
• Interrupt a module in case of fault
• Reconfigure by reading appropriate partial
  bitstreams from memory to ICAP
• Enable/disable signals routed through RSBI
• Compile and Link in XPS
• Generate ELF (Executable Link Format) to program
  FPGA

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Healing Scenarios (II)
2. Hardware failure of one functional module A
which results in the activation of another module
with same functionality A
1. FPGA with a static module and an active
functional module A
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Integrated System (I and II)

• A node breakdown occurs when
• all hardware redundancies get used up and
• node is unable to heal itself through partial
  configuration
• Master then re-assigns that task to another FPGA

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Mission Control GUI

• Image Processing
• Raw image
• Post-processed (DCT)
• Post-processed (DWT)
• Post-processed (FFT)
• Post-processed (CST)
• Post-processed (IMS)
• Real-time Node health status
• Real-time Task Loading
• Who is doing which task/function?
• How fast are they doing it?
• Real-time Network Topology Viewer
• GUI communicates with the base node via serial
  connection 19.2kbps

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MCP GUI
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MCP GUI
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Questions