Architectures for Baseband Processing in Future Wireless Base-Station Receivers

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Architectures for Baseband Processing in Future
Wireless Base-Station Receivers

• Sridhar Rajagopal
• ECE Department
• Rice University
• March 22,2000

This work is supported by Nokia, Texas
Instruments, Texas Advanced Technology Program
and NSF
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Third Generation Wireless
First Generation Voice Eg AMPS
Second/Current Generation Voice Low-rate Data
(9.6Kbps) Eg IS-95(N-CDMA)
Third Generation Voice High-rate Data (2
Mbps) Multimedia W-CDMA
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Main Parts of Base-Station Receiver

• Channel Estimation
• Noise, MAI
• Attenuation
• Fading
• Detection
• Detect users information
• Multiple Users
• Decoding
• Coding/Decoding improve error rate Performance
• Coding done at handset

Wireless Communication Uplink
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Base-Station Receiver
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Need for Better Architectures

• Current DSPs need orders of magnitude
  improvement to meet real-time requirements.
• Reason
• Sophisticated Algorithms, Computationally
  Intensive Operations
• Floating Point Accuracy
• Solution
• Try sub-optimal/iterative schemes
• Fixed Point Implementation
• Use structure in the algorithms
• Parallelism / Pipelining
• Task Partitioning
• Bit Level Arithmetic

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Channel Estimation - An example

• Channel Estimation includes
• Matrix Correlations, Matrix Inversions,
  Multiplications
• Floating Point Accuracy
• Need to wait till all bits are received.
• Modified Channel Estimation Algorithm
• Matrix Inversion eliminated by Iterative Scheme
• Based on Gradient / Method of Steepest Descent
• Negligible effect on Bit error Performance
• Fixed Point accuracy, Computation spread over
  incoming bits
• Features to support Tracking over Fading Channels
  easily added.

Maximum Likelihood Based Channel Estimation
C.Sengupta et al. PIMRC1998, WCNC1999
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Simulations - AWGN Channel
Detection Window 12 SINR 0 Paths 3
Preamble L 150 Spreading N 31 Users K
15 10000 bits/user
MF Matched Filter ML- Maximum Likelihood ACT
using inversion
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DSP Implementation

• Advantages
• Programmability
• Ease of implementation
• High Performance
• Low Cost
• Disadvantages
• Improvements necessary to meet real-time
  requirements!
• Sequential Processing
• Parallelism not fully exploited
• Cannot process or store data at granularity of
  bits.

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VLSI Implementation

• Task Partition Algorithm into Parallel Tasks
• Take Advantage of Bit Level Operations
• Find Area-Time Efficient Architecture
• Meets Real-Time Requirements!

Task A
Task C
Task B
Time
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Conclusions

• Better Performance achieved by
• Modifications in the Algorithm
• Application Specific Architectures
• Algorithmic Modifications
• reduce the complexity of the algorithms
• develop sub-optimal or iterative schemes.
• Custom hardware solutions
• bit level operations and parallel structure.
• Together, algorithm simplifications and custom
  VLSI implementation can be used to meet the
  performance requirements of the Base-Station
  Receiver.

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Future Work

• Analysis for Detection and Decoding
• Mobile Handsets
• Mobile handsets have similar algorithms
• Need to account for POWER too.
• General Purpose Enhancements But, VLSI first
• Explore Instruction Set Extensions /
  Architectures for DSPs
• Exploit Matrix Oriented Structures
• Bit Level Support
• Complex Arithmetic

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Fading Channel with Tracking
Doppler Frequency 10 Hz, 1000 Bits,15 users, 3
Paths
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Talk Outline

• Introduction
• Need for better Architectures
• Channel Estimation - An example
• Simulation Results
• Implementation Issues
• General Purpose/Application Specific
• Conclusions
• Future Work