Ultra Low Power SRAM Design

1
Ultra Low Power SRAM Design

• YODA
• 2/18/05

2
Goal of This Work

• Explore the minimum supply voltage of SRAM
  operation.
• SRAM Data Retention Voltage (DRV) modeling based
  on process variation and design parameters
• Develop design solutions to minimize the SRAM
  operation voltage bound .
• ULV SRAM design optimizations
• Error-tolerant SRAM design

3
Components

• SRAM Data Retention Voltage (DRV) Analysis
• SRAM design optimization for ULV standby
• Huifang, James, Thuan
• Error-tolerant SRAM design
• Huifang, Animesh, Ranjeet, Hsin-I
• ULV operational SRAM
• Huifang, Tim

• SRAM Data Retention Voltage (DRV) Analysis
• SRAM design optimization for ULV standby
• Error-tolerant SRAM design
• ULV operational SRAM

4
Motivation I For the Future of SRAM Design

• Voltage scaling
• Technology driven
• Effectively reduces
• power consumption

SRAM
SOC LP Application
Question How to design SRAM for ULV operation?
5
Motivation II SRAM Leakage Suppression

• On chip SRAM contains 50-90 of total transistor
  count
• Itanium 2 144M/220M
• Charm chip of Picoradio 510K/920K

Logic

• Solution Reduce the standby supply voltage!

SRAM
Itanium 2 Chip
(Figure courtesy of Intel)
6
ULV SRAM - Our Approach

• Model the minimum VDD of SRAM state preservation
• Based on process variation and design parameters

DRV Distribution From Measurement

• Develop design solutions to minimize the SRAM
  operation voltage bound .
• ULV SRAM optimizations
• Error-tolerant SRAM design

7
The Data-Retention Voltage (DRV) of SRAM
DRV Condition

• When Vdd is reduced to DRV, the Voltage Transfer
  Curves (VTC) of the internal inverters degrade to
  such a level that Static Noise Margin (SNM) of
  the SRAM cell reduces to zero.

8
Modeling SRAM DRV
DRV analytical model for any individual cell
where DRV0 is from a variation-free SRAM cell at
27ºC ß is transistor (W/L) ratio.

• Process variation is the main factor that
  determines DRV

9
4KB SRAM Test Chip To See The Real DRV
1.4 mm
IP Module of 4kB SRAM
1.4 mm
Test chip in 0.13um technology
10
SRAM Measurement Results
SRAM Standby VDD

• Measured DRV 60mV 390mV
• (0.13 mm CMOS, 300mV Vth)

• 85 reduction in leakage power with 490mV
  standby Vdd (100mV guard band).

H. Qin, Y. Cao, D. Markovic, A. Vladimirescu, and
J. Rabaey, "SRAM leakage suppression by
minimizing standby supply voltage," Best Paper
Award at ISQED 2004
11
Outline

• SRAM Data Retention Voltage (DRV)
• SRAM design optimization for ULV standby
• Error-tolerant SRAM design
• ULV operational SRAM

12
Low Leakage SRAM Optimization
PMOS 0.16u / 0.145u NMOS 0.23u / 0.13u Pass T
0.16u / 0.16u
V
DD
0
0
M
M
3
1
V2 VDD
M
V
M
5
0
DD
V1 0
6
M
M
Other variables Vth and bitline voltage
4
2
Read Stab.
Write Stab.
13
90nm SRAM Optimization Test Chip

• 64 SRAM arrays, each with different sizing (256
  cells in each array)
• Flexible control on
• Standby BL voltage
• PN body bias
• Array leakage meas.

Chip taped out Oct. 2004
14
Outline

• SRAM Data Retention Voltage (DRV)
• SRAM design optimization for ULV standby
• Error-tolerant SRAM design
• ULV operational SRAM

15
Measured DRV Spatial Distribution

• Measurement result of a 32k bit SRAM test chip
• Block boundary effect is obvious.

16
Error Tolerant SRAM Design

• Guard ring
• Around each SRAM block to prevent boundary effect
• Error correction code (ECC)
• Soft errors protection at the same time

• Goal of ECC design
• Minimize Power
• Min. area overhead
• Max. correction rate
• Minimize coding / decoding complexity and latency

SRAM Chip DRV
17
ECC Space Overview
Long Viterbi decoding latency Low code rate
Block Code
Convolutional Code
LDPC
Turbo Code
Effective for random errors
Reed-Solomon (Comm.)
Long Hamming (memory)

• Requires memory
• Long latency
• Good for
• Low SNR (Dense error)
• Code rate Rlt(2/3)
• (Area OHgt100)

Good at burst error correction
Short Hamming Code
Less power area overhead
Simpler Coding
Lower DRV
18
Hamming Code Vs. Reed-Solomon Code

• 20 leakage power saving
• At 18 area overhead
• Slower decoding (column ECC)
• Smaller active power (32 bits read)

• 25 leakage power saving
• At 25 area overhead
• Faster decoding (row ECC)
• Higher active power (128 bits read)

19
Outline

• SRAM Data Retention Voltage (DRV)
• SRAM design optimization for ULV standby
• Error-tolerant SRAM design
• ULV operational SRAM

20
ULV SRAM Operation
PMOS 0.16u / 0.145u NMOS 0.23u / 0.13u Pass T
0.16u / 0.16u
VDD
VDD
VDD
M
M
3
1
V1 0
M
V2 VDD
V
M
5
0
DD
6
M
M
4
2
Write
Read

• Read and write reliabilities are the top
  challenges!
• Power performance tradeoff follows

21
ULV Operation Noise Margins
v2
ULV SRAM design tradeoff Power Vs. Reliability
Speed
22
ULV Performance Tradeoff with VDD
SRAM Cell Read Delay Vs. VDD
100ns, 400mV
25ns, 500mV
2ns, 1V
SRAM delay is measured at slow corner
23
Error-tolerant ULV SRAM A Practical Solution
STBY
VDD 200mV
BL Control
SC Conv.

1V
ECC Coding
DATA IN
Optimized SRAM cell for ULV operation
ADDR
STBY
Pbb
Charge Pump

Nbb

SA
SA
SA
SA
ECC Decoding Error correction
DATA OUT