Lecture 10: Pipeline Hazards

1
Lecture 10 Pipeline Hazards

• Last Time
• Microarchitecture Summary
• Datapath Control
• Intro to Pipelining
• Today
• Multicycle instructions
• Data and Control Hazards

2
Multicycle Instructions
Cycle
F
R
X1
M
W
X2
X3
F
R
X1
M
W
X2
X3
F
R
X1
M
X2
X3
Instruction
F
R
X
M
W
F
R
X1
X2
F
R
X1
3
Pipeline Hazards

• Data hazards
• an instruction uses the result of a previous
  instruction (RAW)
• ADD R1, R2, R3 or SW R1, 3(R2)
• ADD R4, R1, R5 LW R3, 3(R2)
• Control hazards
• the location of an instruction depends on a
  previous instruction
• JMP LOOP
• LOOP ADD R1, R2, R3
• Structural hazards
• two instructions need access to the same resource
• e.g., single memory shared for instruction fetch
  and load/store
• collision in reservation table

4
Data Hazards (RAW)
Cycle
F
R
X
M
W
Write Data to R1 Here
F
R
X
M
W
Instruction
Read from R1 Here
ADD R1, R2, R3 ADD R4, R1, R5
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Types of Data Hazards

• RAW (read after write)
• only hazard for fixed pipelines
• later instruction must read after earlier
  instruction writes
• WAW (write after write)
• variable-length pipeline
• later instruction must write after earlier
  instruction writes
• WAR (write after read)
• pipelines with late read
• later instruction must write after earlier
  instruction reads

F
R
1
2
3
4
W
F
R
1
2
3
4
R
5
W
6
Pipeline Stalls

• Can resolve any type of hazard
• data, control, or structural
• Detect the hazard
• Freeze the pipeline up to the dependent stage
  until the hazard is resolved

7
An Example Pipeline Stall
ADD R1, R2, R3 ADD R4, R1, R5
IP
IP
4
RW
A
IR
Reg File
I-Mem
D-Mem
C
E
A
A
DO
DO
B
D
DI
IR
IR
IR
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Example Pipeline Stall (Diagram)
Cycle
F
R
X
M
W
Write Data to R1 Here
F
R
X
M
W
Bubble
Instruction
Read from R1 Here
ADD R1, R2, R3 ADD R4, R1, R5
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Implementing Stalls
IRR.RS1

• Detect the stall condition
• comparator on IR fields
• Freeze stalled instructions in place
• recycle pipeline registers
• Invalidate contents of pipeline registers in
  bubble
• valid bit
• The process of allowing an instruction to proceed
  because all dependencies are satisfied is often
  called issuing the instruction

OR
Stall
IRA.RD
Stall
V
Stage
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Stalls and CPI
Where fi is fraction of instructions that stall
for i cycles
Example 50 of instructions are dependent on the
next instruction 30 of the remaining
instructions are dependent on the instruction
after next C (1 x .2) (2 x .3) (3 x .5) 2.3
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Bypass (Forwarding)

• If data is available elsewhere in the pipeline,
  there is no need to stall
• Detect condition
• Bypass (or forward) data directly to the
  consuming pipeline stage
• Bypass eliminates stalls for single-cycle
  operations
• reduces longest stall to N-1 cycles for N-cycle
  operations

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Simple Pipeline with Bypass Multiplexers
IP
IP
4
RW
A
IR
Reg File
I-Mem
D-Mem
C
E
A
DO
A
DO
B
D
DI
IR
IR
IR
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Example Execution with Bypass
ADD R1, R2, R3 ADD R4, R1, R5
IP
IP
4
RW
A
IR
Reg File
I-Mem
D-Mem
C
E
A
DO
A
DO
B
D
DI
IR
IR
IR
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Control of Bypass

• Compare source register fields of IRX to
  destination register fields of IRM and IRW.
• If match and fields active, enable appropriate
  bypass path

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Control Hazards (Conditional Branch)
Cycle
F
R
X
M
W
Branch Test and Destination
F
R
X
M
W
Instruction
Need Destination Here
JR R25 ... XX ADD ...
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Reducing Control Hazards
Cycle
F
R
X
M
W
Branch Test and Destination
F
R
X
M
W
Instruction
Need Destination Here
JR R25 ... XX ADD ...
Move test logic into R stage
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Branch Delay Slots

• Since we need to have a dead cycle anyway, lets
  put a useful instruction there
• Advantage
• Do more useful work
• Disadvantage
• Exposes microarchitecture to ISA

ADD R2,R3,R4BNEZ R5,_loop NOP
BNEZ R5,_loop ADD R2,R3,R4
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Control Hazards

• Conservatively, the pipeline waits until the
  branch target is computed before fetching the
  next instruction.
• Alternatively, we can speculate which direction
  and to what address the branch will go.
• Need to confirm speculation and back up later.

F
R
X
M
W
F
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Example Speculative Conditional Branch
BNEZ R1, LOOP ADD R2, R3, R4 SUB R5, R6, R7
IP
IP
4
RW
A
IR
Reg File
I-Mem
D-Mem
C
E
A
DO
A
DO
B
D
DI
IR
IR
IR
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Speculative Conditional Branch (Diagram)
Cycle
BNEZ R1, LOOP ADD R2, R3, R4 SUB R5, R6, R7
F
R
X
M
W
Condition and Dest Available Here
F
R
X
M
W
Instruction
F
R
X
M
W
Speculate Not Taken
Confirm or Branch
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Summary

• Today
• Multicycle instructions
• Data and Control Hazards
• Next Time
• Put it all together
• Advanced Pipelining Instruction-level
  parallelism