Regular Expression Manipulation FSM Model

1
Regular Expression ManipulationFSM Model

• Sequential Machine Theory
• Prof. K. J. Hintz
• Department of Electrical and Computer Engineering
• Lecture 6

Modifications by Marek Perkowski
2
Null Machine

• 3 Methods for Proving That a Machine Accepts No
  Words
• By inspection
• Any path from the start state to a final state
  means that at least one word is accepted by the
  machine
• By state diagram manipulation
• If a final state is relabeled as a start state,
  then the machine must accept at least one word

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Null Machine

• By converting the regular expression into a
  deterministic FA
• If possible, FA must accept at least one word
• Conversion to FA may not be possible
• Machine may have no final states.
• There is no path from the initial state to any
  final state.

4
State Diagram Manipulation

• A procedure to determine if a machine accepts no
  strings
• Remove all edges (arrows) to the start state.
• From the start state, identify all single-step
  next states.
• Relabel these next states as start states and
  eliminate the edges used to get there.
• go to (b)
• If a final state is relabeled as a start state,
  then the machine must accept at least one word.

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State Diagram Manipulation

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State Diagram Manipulation

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State Diagram Manipulation

• Does Not Accept Any
• Word Since
• There Is No
• Path From
• - To .

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The Complement Machine

• A Complement Machine Accepts All Expressions
  Other Than Those Accepted by the Original Machine
• Method
• Change all non-final states into final states
• Change all final states into non-final states
• Leave start state unchanged

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Language Decidability

• Methods for Determining If Two Regular
  Expressions Define the Same Language
• Language Enumeration with 11 correspondence
  between the 2 languages.
• The regular languages can be accepted by
  identical FAs.
• Generate

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Language Overlap

• If the Overlap Language Is NOT the Null Set, Then
  There Is Some Word in L1 Which Is Not Accepted by
  L2 and Vice Versa.
• If the Overlap Language Accepts the Null String,
  Then the Languages Are Not Equal.

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DeMorgans Theorem

• Applies Equally Well to Sets As Well As Boolean
  Algebra

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Regular Expression Equivalence

• Methodology
• Construct the complement machines
• Apply DeMorgans theorem since it is difficult to
  form the intersect machine

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Regular Expression Equivalence

• Take the Unions of the Complemented and
  Non-complemented Several Times to Determine
  Whether Loverlap Is the Null Set or Not

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RE Equivalence Example

• Two REs are represented by their equivalent FAs
  (FA1 does FA2)

Cohen, Prob. 2, page 233.
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RE Equivalence Example

• Form the Complement Machines

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RE Equivalence Example

• Make the Product Machine of FA2 and the
  Complement of FA1.

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RE Equivalence Example

• States of Product Machine, FA1-bar FA2
• Only One Start State / Multiple Final States

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RE Equivalence Example

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Product Machine State Table
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State Diagram of Product

• FA1-Bar, FA2

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Reduced State Diagram

• Non-Reachable States Removed

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RE Equivalence Example

• Take the Complement Of the Union by changing
  final states to non-final and vice-versa
• No Final States, So Complement FA Accepts No Words

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RE Equivalence Example

• Do the Same for the Right Term of Loverlap

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RE Equivalence Example

• Application of Same Procedure to Preceding
  Machine Also Results in No Recognizable Words.
• Since Both Terms of Loverlap are Null, Then REs
  Are Equivalent Since Their Union Is Null.

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Moore Mealy Machines

• The Behavior of Sequential Machines Depends on
  Previous Inputs.
• Moore Machine
• Output only depends on present state
• Mealy Machine
• Output depends on both the present state and the
  present input

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Moore Mealy Machines

• Equivalent Descriptive Methods
• Transition (state) table
• Transition (state) diagram
• Operational descriptions using set theory
• (Language recognized by the machine)

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Moore Machine
Input
Present State
Output
Output Is Only a Function of Present State
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Primitive State Diagram, Moore
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Moore Machine State Diagram
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Mealy Machine
Input
Present State
Output
Output Is Function of Present State AND Present
Input
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Primitive State Diagram, Mealy
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Mealy Machine State Diagram
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Transition Table

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FSM Design Approaches

• One-Hot
• One flip-flop is used to represent each state
• Costly in terms of discrete hardware, but trivial
  to design
• Efficient in FPGAs because FF part of each CLB
• Binary Coded State
• n flip-flops used to store 2n states
• Most efficient
• Need to account for unused states

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FSM and Clocks

• Synchronous FSMs may change state only when a
  unique input, the clock, occurs
• Asynchronous FSMs may change state when input
  changes
• Next state depends on present input and present
  state for both Moore and Mealy

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Synchronous versus Asynchronous Machines in Design

• Synchronous FSMs
• Easier to design, turn the crank
• Slower operation
• Asynchronous
• Harder to design because of potential for races,
  iterative solutions
• Faster operation

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Mealy 0101 Detector

• M ( S, I, O, d, b )
• S A, B, C, D
• I 0, 1
• O 0, 1 not detected, detected
• d next slide
• b next slide

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Mealy Transition/Output Table
Next State/Output
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0101 State Diagram
1/0
0/0
0/0
1/0
0/0
1/0
1/1
0/0
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Moore 0101 Detector

• M ( S, I, O, d, l )
• S A, B, C, D, E
• I 0, 1
• O 0, 1 not detected, detected
• d next slide
• l next slide

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Moore Transition/Output Table
Next State
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Moore 0101 State Diagram
0
1
0 detected
0
A/0
B/0
0
1
1
1
0
C/0
0
1
01 det
0101 det
010 det
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Asynchronous FSM

• Fundamental Mode Assumption
• Only one input can change at a time
• Analysis too complicated if multiple inputs are
  allowed to change simultaneously
• Circuit must be allowed to settle to its final
  value before an input is allowed to change
• Behavior is unpredictable (nondeterministic) if
  circuit not allowed to settle

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Asynch. Design Difficulties

• Delay in Feedback Path
• Not reproducible from implementation to
  implementation
• Variable
• may be temperature or electrical parameter
  dependent within the same device
• Analog
• not known exactly

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Stable State

• PS present state
• NS next state
• PS NS Stability
• Machine may pass through none or more
  intermediate states on the way to a stable state
• Desired behavior since only time delay separates
  PS from NS
• Oscillation
• Machine never stabilizes in a single state

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Races

• A Race Occurs in a Transition From One State to
  the Next When More Than One Next State Variables
  Changes in Response to a Change in an Input
• Slight Environment Differences Can Cause
  Different State Transitions to Occur
• Supply voltage
• Temperature, etc.

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Races
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Types of Races

• Non-Critical
• Machine stabilizes in desired state, but may
  transition through other states on the way
• Critical
• Machine does not stabilize in the desired state

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Races
PS
if Y2 changes first
if Y1 changes first
desired NS non- critical race
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Asynchronous FSM Benefits

• Fastest FSM
• Economical
• No need for clock generator
• Output Changes When Signals Change, Not When
  Clock Occurs
• Data Can Be Passed Between Two Circuits Which Are
  Not Synchronized
• In some technologies, like quantum, clock is just
  not possible to exist

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Asynchronous FSM Example
input
next state
present state
y1
y2
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Next State Variables
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Sequential Machines Problems

• Three Problems of Sequential Machines
• State minimization problem
• Determine all equivalent states of a sequential
  machine, and,
• Eliminate redundant states
• Machine Decomposition
• Separate large machines into an interconnected
  set of smaller machines
• Easier to design and analyze small machines

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Sequential Machine Problems

• State assignment problem
• There is no guidance on which binary number to
  assign to which state in a primitive state table
• Complexity of implementation is dependent on
  mapping of states to binary numbers
• Unsolved problem
• Design all machines and compare
• Benefit of decomposition of large machine into
  smaller machines.

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Set Theoretic Description

• Moore Machine is an ordered quintuple

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Set Theoretic Description

• Mealy Machine is an ordered quintuple

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Recursive Definitions of Delta

• State Transition for Moore Mealy
• Single-valued, else not deterministic.
• At least a partial function
• Not necessarily injective or surjective
• Shields nomenclature

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Recursive Definitions of Delta

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Recursive Definitions of Beta

• Causal, No Output for No Input.
• For a Given Input Sequence, There Will Be a
  Deterministic Output Sequence of the Same Length
  As the Input.

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Recursive Definitions of Lambda

• Same Caveats As Beta

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