New approaches to hardware synthesis

1
New approaches to hardware synthesis Byron
Cook and Satnam Singh with Ashutosh Gupta,
Stephen Magill, Andrey Rybalchenko, Jiri Simsa,
and Viktor Vafeiadis
2
Beyond proving correctness

• Program verification impossible 10 years ago,
  standard today
• SLAM, SLAyer, TERMINATOR, etc
• Complexity analysis, WP synthesis, WLP synthesis,
  etc
• Can we use these techniques elsewhere?
• Compilers ?
• Operating systems?
• Language runtimes?
• Current focus hardware synthesis
• Heap-based programs
• Automatically parallelized circuits
• Aggressive unrolling

3
Beyond proving correctness

• Program verification impossible 10 years ago,
  standard today
• SLAM, SLAyer, TERMINATOR, etc
• Complexity analysis, WP synthesis, WLP synthesis,
  etc
• Can we use these techniques elsewhere?
• Compilers ?
• Operating systems?
• Language runtimes?
• Current focus hardware synthesis
• Heap-based programs
• Automatically parallelized circuits
• Aggressive unrolling

4
Beyond proving correctness

• Program verification impossible 10 years ago,
  standard today
• SLAM, SLAyer, TERMINATOR, etc
• Complexity analysis, WP synthesis, WLP synthesis,
  etc
• Can we use these techniques elsewhere?
• Compilers ?
• Operating systems?
• Language runtimes?
• Current focus hardware synthesis
• Heap-based programs
• Automatically parallelized circuits
• Aggressive unrolling

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Heap-bounds
6
Heap-bounds
7
Heap-bounds
8
Heap-bounds
9
Heap-bounds
10
Heap-bounds
11
Heap-bounds
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Altera DE2 FPGA Board
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Altera synthesis/implementation tools
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Synthesized logic
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Prio layout on FPGA chip
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VHDL simulation of prio netlist
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Logic analyzer output
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Conclusion

• Big advances in formal verification, analysis,
  understanding
• Alternative uses for these new techniques?
• Compiling for embedded systems or hardware?
• Automatic parallelization?
• Speculative execution and rollback?
• Mixed static/dynamic property checking in
  runtimes?
• Runtime verification of progress (i.e.
  termination)?
• Current project
• Solving open problems in hardware synthesis
• Further blurring the line between hardware and
  software
• Demo first-known synthesis tool supporting
  dynamic heap
• Note no optimization done yet lots of room for
  improvement