Reconfigurable Computing High Level Specification, Modeling and Synthesis of RunTime Reconfigurable

1
Reconfigurable ComputingHigh Level
Specification, Modeling and Synthesis of Run-Time
Reconfigurable Systems

• S. Arun Nair
• Under the supervision of
• Dr. Kolin Paul

2
Outline

• Objectives
• Introduction
• Reconfiguring FPGA
• Xilinx PR Design Flow
• Runtime Reconfiguration - An Example
• The Molen Prototype
• Self Reconfiguration ICAP
• Project Status

3
Objectives

• To understand the Run Time Reconfiguration issues
  by implementing Runtime Reconfigurable systems
  using the Xilinx FPGA Fabric.
• Using this understanding to bring formalism in
  specification of such systems.

4
Introduction

• Virtex-II and Virtex-II Pro allow for Partial
  Reconfiguration.
• Time-sharing of multiple design modules.
• Enables small sections of large systems to run
  simultaneously
• System must be reducible to small sections
• Only a small number of these sections active at a
  time.

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Terminology (1/2)

• Reconfiguration
• Partial Reconfiguration
• Active/Runtime
• Shutdown
• Partial Reconfiguration Module/Region
• Area Group
• Constraint
• Range Constraint

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Terminology (2/2)

• Base Design
• Bus Macros
• Pre-placed and Pre-routed
• Make PRMs pin compatible
• with Base Region.
• Synchronous/Asynchronous
• l2r and r2l

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Reconfiguration Strategies

• Static Reconfiguration
• Dynamic Reconfiguration
• Runtime Reconfiguration
• Better utilization of Resources
• Self Reconfiguration
• Dynamic Reconfiguration
• Part of the FPGA logic used for Reconfiguration

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Reconfiguring FPGA

• Different Configuration interfaces
• JTAG
• SelectMAP
• Slave/Master Serial
• ICAP (a special case of SelectMAP)
• Different Configuration phases
• Clearing the configuration memory
• Initialization
• Bitstream Loading
• Device Startup

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Xilinx PR Design Flow
Module Design Verilog or VHDL
Timing, IOs
Automated using PlanAhead Software
Synthesis of Each Module

• Synthesize PRMs and Static Modules separately.
• Place and Route these modules.
• Merge the two parts of the system.

Bit Stream Generation and upload on FPGA
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Runtime Reconfiguration An Example

• Design consists of two parts
• Fixed Logic (Base Design)
• PRMs
• Base design can be divided into
• Top Module
• Control Module
• UART Transceiver module

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Runtime Reconfiguration An Example

• There are two PRMs mapped to a PRR
• Subtractor Module
• Adder Module

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Runtime Reconfiguration An Example
PRM
Control Module
Bus Macros
UART Modules
RTL Schematic of the Design
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Example Top Module

• Contains no logic
• Instantiates all modules
• Defines Interconnects
• 2 l2r bus macros
• 1 r2l bus macro
• Clock Buffer

entity top is Port ( clk in std_logic rx in
std_logic tx out std_logic ) end top
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Example Control Module

• State machine that describes system behaviour

entity control is Port ( clk in
std_logic data_to_op out std_logic_vector(3
downto 0) instruction_to_op out
std_logic_vector(1 downto 0) data_from_op in
signed(7 downto 0) op_id in std_logic write_tx
out std_logic din_tx out std_logic_vector(7
downto 0) data_present_rx in
std_logic read_rx out std_logic dout_rx in
std_logic_vector(7 downto 0) ) end control
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Example-Control Module

• State0 wait for data to be present on serial
  interface.
• State1 Determine what to do, depending on
  input.
• State2 to State4 Answer query about current
  flavour.
• State5 to State11 Compute result and send it
  back.
• State12 to State19 Print error messages, read
  new pair of inputs.

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Example Adder/Subtractor Module

• Read two operands
• Add or Subtract
• Return the result
• Maintain current flavour

entity rModule is Port ( clk in
std_logic instruction_in in std_logic_vector(1
downto 0) data_in in std_logic_vector(3 downto
0) data_out out signed(7 downto 0) id out
std_logic) end rModule
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Example UART Module

• Transmit data off chip
• Receive data on Serial Interface
• 3 constituent modules
• uart_baudClock_inst convert chip clock to UART
  9600 baud rate.
• uart_tx_inst transmit data out of UART port.
• uart_rx_inst receive data from UART port.

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The Molen Prototype

• Reconfigurable design platform.
• Based on Xilinx Virtex II Pro platform.
• Custom Computing Units (CCU).
• ISA ? pISA.
• Core processor (PPC) Reconfigurable Processor.
• Accelerating specific code sections, using RP.

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The Molen Prototype
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Molen Machine Organization
Molen machine organization
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Exchange Registers

• The Exchange Registers
• movtx Register File ? XREGs
• movfx XREGs ? Register File
• All parameters of an operation in
• consecutive XREG locations
• Default XREG read by the
• microcode contains block address

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Compiler

• Compiler Features
• Code identification
• Instruction Set Extension
• Register File Extension
• Code Generation

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Compiler
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Essential Port Structure

• Port(
• RST in std_logic
• clk in std_logic
• CCU_clk in std_logic
• start_op in std_logic
• MIR in std_logic_vector(c_MIR-1 downto 0)
• end_op out std_logic
• status out std_logic_vector(c_STATUS-1 downto
  0)
• XREG_addr out std_logic_VECTOR(9 downto 0)
• XREG_WR_DBus out std_logic_VECTOR(31 downto 0)
• XREG_RD_DBUS in std_logic_VECTOR(31 downto 0)
• XREG_write out std_logic
• data_addr out std_logic_vector(c_RMDADDR-1
  downto 0)
• brw out std_logic_vector(c_BRW-1 downto 0)
• write_data out std_logic_vector(63 downto 0)
• read_data in std_logic_vector(63 downto 0))

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Molen - Example

• FSM read arguments and store in registers
• Provide address
• Read data
• Repeat until all arguments read

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Example Copy Array

• Copy elements from A to X
• Get address for Ai and Bi
• Copy Ai to Xi
• Repeat until A is exhausted

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Self Reconfiguration

• Motivation
• Stand alone systems
• Lower reconfiguration latency
• Self modifying based on external stimulus
• H/W support
• ICAP, JTAG
• S/W support
• HWICAP on Xilinx Platforms

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ICAP

• Internal Configuration Access Port
• Support for Partial Reconfiguration
• Subset of SelectMAP
• Does not allow full configuration

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OPB_HWICAP Module

• Wraps ICAP with additional logic for read/write
  control.
• Interfaces with CoreConnect OPB.

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Read-Modify-Write

• Read configuration frame one at a time
• Store them in BRAMs
• Modify the frame
• Write it back using ICAP

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Project Status/Deliverables

• Literature Survey/Familiarization.
• Built a small Reconfigurable System.
• Tested Molen Prototype.
• Self Reconfiguration on Xilinx Platform is being
  studied.